Details, datasheet, quote on part number: FPD87310
CategoryOptoelectronics => Drivers/Controllers => LCDs => Flat Panel
TitleFlat Panel
DescriptionUniversal Interface Xga Panel Timing Controller With RSDS (reduced Swing Differential Signaling) And Fpd-link
CompanyNational Semiconductor Corporation
DatasheetDownload FPD87310 datasheet
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Features, Applications

FPD87310 Universal Interface XGA Panel Timing Controller with RSDSTM (Reduced Swing Differential Signaling) and FPD-Link

The FPD87310 Panel Timing Controller is an integrated FPD-Link + RSDS + TFT-LCD Timing Controller. It resides on the Flat Panel Display and provides the interface signal routing and Timing Control between Graphics or Video Controllers and a TFT-LCD system. FPD-Link, a low power, low EMI (ElectroMagnetic Interference) interface is used between this Controller and the Host system. A RSDS (Reduced Swing Differential Signaling) Column Driver interface is used between the Timing Controller and the Column Drivers. Programmable, General Purpose Outputs provide Row and Column Driver control. The FPD87310 is configured via metal mask initialization value or an optional external serial EEPROM. Reserved space in the EEPROM is available for display identification information. The system can access the EEPROM to read the display identification data or program initialization values used by the FPD87310. This single 9-bit+CLK differential bus conveys the 18 bits color data for XGA panels at 130 Mb/s when using VESA 60 Hz standard timing.


n RSDS (Reduced Swing Differential Signaling) Column Driver bus for low power and reduced EMI n Drives RSDS Column Drivers at 130 Mb/s with a 65 MHz clock or 8-bit LVDS Video System Interface (FPD-Link) n 10 General Purpose Outputs for Column/Row Drivers n Optional EEPROM programming allows fine tuning in development and production environments n Selectable dual initialization value sets to share parts for the different model panel module n Ability to drive XGA/SVGA TFT-LCD Systems n Narrow 9-bit+CLK differential Column Driver Bus minimizes width of Source PCB n CMOS circuitry operates from a 3.3V supply n Supports Graphics Controllers with spread spectrum interface featurefor lower EMI

TRI-STATE is a registered trademark of National Semiconductor Corporation.

If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VDD) DC Input Voltage (VIN) DC Output Voltage (VOUT) Storage Temperature Range (TSTG) Lead Temperature (TL) (Soldering 10 sec.) -0.3V to VDD +150C 260C

Supply Voltage (VDD) Operating Temp Range (TA) Operating Frequency (fCLK) Min 3.0 0 Max Units C 67 MHz

DC ELECTRICAL CHARACTERISTICS VDD 0.3V, VSS = 0.0V (Unless otherwise specified). Symbol VOH VOL VIH VIL IIN IDD Parameter Minimum High Level Output Voltage Maximum Low Level Output Voltage Minimum High Level Input Voltage Maximum Low Level Input Voltage Input Current Supply Current VIN = VSS to VDD fCLK = 65 MHz, RPI = 13k, See Figure 1 -10 Conditions VDD = 3.3V, IOH 8 mA VDD = 3.3V, IOL 8 mA Min 2.2 0.8 Typ Max Units A mA

FPD-Link (LVDS) RECEIVER INPUT (RxCLK+/-, RxIN[y]+/-; y Symbol VIHLVDS VILLVDS VCMLVDS IIN Parameter LVDS Input High Level Threshold Voltage LVDS Input Low Level Threshold Voltage LVDS Input Common Mode Voltage Range LVDS Input Current Conditions VCMLVDS = +1.2V (Note 2) VCMLVDS = +1.2V (Note 2) VDIFFLVDS 100 mV (Note 2) VIN = +2.4V, VCC = 3.6V VIN = 0V, VCC = 3.6V RSDS TRANSMITTER OUTPUT (RSCKP/N, RSx[y]P/N; B y Symbol VOHRSDS VOLRSDS VCMRSDS Parameter RSDS High Differential Output Voltage RSDS Low Differential Output Voltage RSDS Common Mode Output Voltage Conditions VCMRSDS 5% (Note 3) VCMRSDS 5% (Note 3) VDIFFRSDS 200 mV (Note 3) Min +150 Typ Max Units -100 1.25 Min Typ Max +100 Units mV V

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics" specifies conditions of device operation. Note 2: VCMLVDS = (VRxCLK+ VRxCLK-)/2 or VCMLVDS = (VRxIN[y]+ VRxIN[y]-)/2; y VDIFFLVDS = VRxCLK+ - VRxCLK- or VDIFFLVDS = VRxIN[y]+ - VRxIN[y]-; y Note 3: VCMRSDS = (VRSCKP VRSCKN)/2 or VCMRSDS = (VRSx[y]P B y VDIFFRSDS = VRSCKP - VRSCKN or VDIFFRSDS = VRSx[y]P - VRSx[y]N; B y The Termination Resister for differential line between positive and negative output is 100. Pin "PI" is connected to ground 13.0 k. This parameter is Guaranteed by Design.

FPD-Link INPUT TIMING VDD 0.3V, VSS = 0.0V (Unless otherwise specified). Symbol RPLLS RSKM Parameter FPD-Link Receiver Phase Lock Loop Wake-up Time RxIN Skew Margin (Note 4) VDD 25C 400 Conditions Min Typ Max 10 Units ms ps

Note 4: Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account transmitter output skew (TCCS) and the setup and hold time (internal data sampling window) allowing for FPD-Link LVDS cable skew dependent on type/length of cable, and source clock (FPD-Link Transmitter TxCLK IN) jitter. RSKM cable skew (type, length) + source clock jitter (cycle to cycle). The specified RSKM minimum assumes a TPPOSmax limit 200ps (65MHz). This parameter is Guaranteed by Design.

Setup and Hold Time (internal data sampling window) Transmitter Output Skew Cable Skew (type, length) + Source Clock Jitter (cycle to cycle) FIGURE 2. FPD87310 (FPD-Link Receiver) Input Skew Margin


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