Details, datasheet, quote on part number: G1-266B-85-1.8
CategoryCommunication => Telephony => Voice Processors
DescriptionProcessor Series Low Power Integrated X86 Solution
CompanyNational Semiconductor Corporation
DatasheetDownload G1-266B-85-1.8 datasheet
Find where to buy


Features, Applications
GeodeTM GX1 Processor Series Low Power Integrated x86 Solution

The National Semiconductor® GeodeTM GX1 processor series is a line of integrated processors specifically designed to power information appliances for entertainment, education, and business. Serving the needs of consumers and business professionals alike, it's the perfect solution for IA (information appliance) applications such as thin clients, interactive set-top boxes, and personal internet access devices. The Geode GX1 processor series is divided into three main categories as defined by the core operating voltage. Available with core voltages 2.0V, 1.8V, and 1.6V, it offers extremely low typical power consumption (1.2W, 1.0W, and 0.8W, respectively) leading to longer battery life and enabling small form-factor, fanless designs. Typical power consumption is defined as an average, measured running Microsoft Windows at 80% Active Idle (Suspend-on-Halt) with a display resolution of 800x600x8 bpp at 75 Hz.

INTR Core Clocks X-Bus Clocks x86 Compatible Core INT/NMI TLB Integer Unit FP_Error Interrupt Control IRQ13 SMI#

Core Acknowledge X-Bus Suspend X-Bus Acknowledge X-Bus (32) Arbiter X-Bus Controller
Display Controller Compression Buffer Palette RAM Timing Generator

National Semiconductor and Virtual System Architecture are registered trademarks of National Semiconductor Corporation. Geode, WebPAD, and VSA, are trademarks of National Semiconductor Corporation. For a complete listing of National Semiconductor trademarks, please visit

While the x86 core provides maximum compatibility with the vast amount of Internet content available, the intelligent integration of several other functions, such as audio and graphics, offers a true system-level multimedia solution. The Geode GX1 processor core is a proven x86 design that offers competitive performance. It contains integer and floating point execution units based on sixth-generation technology. The integer core contains a single, five-stage execution pipeline and offers advanced features such as operand forwarding, branch target buffers, and extensive write buffering. Accesses to the 16 KB write-back L1 cache are dynamically reordered to eliminate pipeline stalls when fetching operands. In addition to the advanced CPU features, the GX1 processor integrates a host of functions typically implemented with external components. A full function graphics accelerator contains a VGA (video graphics array) controller, bitBLT engine, and a ROP (raster operations) unit for complete GUI (Graphical User Interface) acceleration under most operating systems. A display controller contains additional video buffering to enable >30 fps MPEG1 playback and video overlay when used with a National Semiconductor Geode I/O or graphics companion chip (e.g., or CS9211). Graphics and system memory accesses are supported by a tightly coupled SDRAM controller which eliminates the need for an external L2 cache. A PCI host controller supports up to three bus masters for additional connectivity and multimedia capabilities. The GX1 processor also incorporates Virtual System Architecture® (VSATM) technology. VSA technology enables the XpressGRAPHICS and XpressAUDIO subsystems. Software handlers are available that provide full compatibility for industry standard VGA and 16-bit audio functions that are transparent at the operating system level. Together the National Semiconductor I/O companion and GX1 processor Geode devices provide a scalable, flexible, low-power, system-level solution well suited for a wide array of information appliances ranging from hand-held personal information access devices to digital set-top boxes and thin clients.


Packaging: 352-Terminal Ball Grid Array (BGA) or 320-Pin Staggered Pin Grid Array (SPGA) 0.18-micron four layer metal CMOS process Split rail design: Available or 2.0V core 3.3V I/O interface Fully static design Low Typical Power Consumption: @ 1.6V/200 MHz @ 2.0V/300 MHz Typical power consumption is defined as an average, measured running Windows at 80% Active Idle (Suspend-on-Halt) with a display resolution of 800x600x8 bpp @ 75 Hz.

Speeds offered to 300 MHz Unified Memory Architecture Frame buffer and video memory reside in main memory Minimizes PCB (Printed Circuit Board) area requirements Reduces system cost Compatible with multiple Geode I/O companion devices provided by National Semiconductor

Supports Intel's MMX instruction set extension for the acceleration of multimedia applications 16 KB unified L1 cache Six-stage pipelined integer unit Integrated Floating Point Unit (FPU) Memory Management Unit (MMU) adheres to standard paging mechanisms and optimizes code fetch performance: Load-store reordering gives priority to memory reads Memory-read bypassing eliminates unnecessary or redundant memory reads Re-entrant System Management Mode (SMM) enhanced for VSA technology

Supports a wide variety of standards: APM (Advanced Power Management) for Legacy power management ACPI (Advanced Configuration and Power Interface) for Windows power management ­ Direct support for all standard processor (C0-C4) states OnNOW design initiative compliant Supports a wide variety of hardware and software controlled modes: Active Idle (core-only stopped, display active) Standby (core and all integrated functions halted) Sleep (core and integrated functions halted and all external clocks stopped) Suspend Modulation (automatic throttling of CPU core via Geode I/O or graphics companion chip) ­ Programmable duty cycle for optimal performance/ thermal balancing Several dedicated and programmable wake-up events (via Geode I/O or graphics companion chip)

Accelerates BitBLTs, line draw, text: Bresenham vector engine Supports all 256 Raster Operations (ROPs) Supports transparent BLTs and page flipping for Microsoft's DirectDraw Runs at core clock frequency Full VGA and VESA mode support Special "driver level" instructions utilize internal scratchpad for enhanced performance

Display Compression Technology (DCT) architecture greatly reduces memory bandwidth consumption of display refresh Supports a separate video buffer and data path to enable video acceleration in Geode I/O and graphics companion chips Internal palette RAM for gamma correction Direct interface to Geode I/O and graphics companion chips for CRT and TFT flat panel support eliminates the need for an external RAMDAC Hardware cursor Supports to 1280x1024x8 bpp and 1024x768x16 bpp

Several arbitration schemes supported Directly supports up to three PCI bus masters, more with external logic Synchronous to CPU core Allows external PCI master accesses to main memory concurrent with CPU accesses to L1 cache

SDRAM interface tightly coupled to CPU core and graphics subsystem for maximum efficiency 64-Bit wide memory bus Support for: Two 168-pin unbuffered DIMMs to 16 simultaneously open banks 16-byte reads (burst length of two) 512 MB total memory supported

Innovative architecture allowing OS independent (software) virtualization of hardware functions Provides XpressGRAPHICS subsystem: High performance legacy VGA core compatibility The GUI acceleration is pure hardware.

Provides 16-bit XpressAUDIO subsystem: 16-bit stereo FM synthesis OPL3 emulation Supports MPU-401 MIDI interface Hardware assist provided via Geode I/O companion chip Additional hardware functions can be supported as needed

Microsoft's Windows 2000, Windows 95, Windows 98, and Windows NT in non PC applications; along with Windows CE and Windows NTE WindRiver System's VxWorks QNX Software Systems' QNX Linux


Related products with the same datasheet
Some Part number from the same manufacture National Semiconductor Corporation
G1-266P-85-1.8 Processor Series Low Power Integrated X86 Solution
GD54LS08 54LS08 - Quad 2-Input And Gate, Package: Lcc, Pin Nb=20
GD54LS161A DM54LS161A - Synchronous 4-Bit Binary Counter With Asynchronous Clear, Package: Cerdip, Pin Nb=16
GD54LS175 DM54LS175 - Quad D Flip-flop With Clear And Complementary Outputs, Package: Cerpack, Pin Nb=16
GD54LS32 DM54LS32 - Quad 2-Input OR GATE, Package: Lcc, Pin Nb=20
GEODEGXLVPROCESSORSeries Low Power Integrated X86 Solution
GEODEGXMPROCESSOR Integrated X86 Solution With Mmx(tm) Support
GL-166B-85-2.2 Geode Processor Series Low Power Integrated X86 Solutions
GM-180B-70 Geode Processor Integrated X86 Solution With MMX Support
GS9000 CLC011 - Serial Digital Video Decoder, Package: Plcc, Pin Nb=28
GX1 Geode Processor Series Low Power Integrated X86 Solution
GX9533 CLC018 - 8 X 8 Digital Crosspoint Switch, 1.485 Gbps, Package: Pqfp, Pin Nb=64
GXLV Geode Processor Series Low Power Integrated X86 Solutions
GXM Geode Processor Integrated X86 Solution With MMX Support

DP83223A : DP83223 - Twister High Speed Networking Transceiver Device, Package: Plcc, Pin Nb=28

DS14185MDA :

LM1117DT-1.8 : Positive Voltage->Adjustable LM1117 - 800mA Low-dropout Linear Regulator, Package: to 252, Pin Nb=3

LM34A : Precision Farenheit Temperature Sensor

LMC6572AIN : LMC6572 - Dual Low Voltage (2.7V to 3V) Operational Amplifier, Package: Soic Narrow, Pin Nb=8

LM4040D20IDCKRG4 : Precision Micropower Shunt Voltage Reference

DS90LV031AW-QML : 3V LVDS Quad CMOS Differential Line Receiver

TP5700A : Telephone Speech Circuit

Same catergory

CA3189 : FM if System. [ /Title (CA31 89) /Subject (FM IF System) /Autho r /Keywords (Harris Semiconductor, FM IF amplifier, quadrat ure detector, tuning meter output, limiter, AFC circuit, AGC circuit, muting circuit, industrial tempera- Includes IF Amplifier, Quadrature Detector, AF Preamplifier, and Specific Circuits for AGC, AFC, Tuning Meter, Deviation-Noise Muting,.

EEI16LC12C : Low Capacitance, Bidirectional, Eight Line Monolithic TVS Diode Network.

HC-5509B3999-003 : Slic Subscriber Line Interface Circuit. The HC-5509B3999-003 telephone Subscriber Line Interface Circuit integrates most of the BORSCHT functions on a monolithic IC. The device is manufactured in a Dielectric Isolation (DI) process and is designed for use as a high voltage interface between the traditional telephone subscriber pair (Tip and Ring) and the low voltage filtering and coding/decoding.

HD74LS145P : Bcd-to-decimal Decoders / Drivers ( With 15v Outputs ).

KSM-951LJ34Y : Optic Receiver Module. The KSM-95”ąLJ34Y consist of a PIN Photodiode of high speed and a preamplifier IC in the package as an receiver for Infrared remote control systems DIMENSIONS ¤żOne mold small size package ¤żWide supply-voltage range to 5.5V ¤żShielded against electrical field disturbance ¤żHigh immunity against ambient light disturbances ¤żAvailable for carrier frequencies.

MAX2383EVKIT : MAX2383EVKIT Evaluation Kit For The MAX2383. The MAX2383 evaluation kit (EV kit) simplifies the evaluation of the MAX2383. It includes an LO balun for interfacing with differential LO ports. Similarly, an IF balun is used for interfacing with differential IF ports. SMA connectors are included to facilitate easy connections. o Baluns are Included for Single-Ended LO and IF Drives o All Inputs and Outputs.

MC54HC541AJ : Octal 3-state Non-inverting Buffer/line Driver/line Receiver. Octal 3-State Non-Inverting Buffer/Line Driver/ Line Receiver The MC54/74HC541A is identical in pinout to the LS541. The device inputs are compatible with Standard CMOS outputs. External pullup resistors make them compatible with LSTTL outputs. The is an octal non­inverting buffer/line driver/line receiver designed to be used with 3­state memory address.

MT8979AE : = Cept PCM 30/CRC-4 Framer & Interface ;; Package Type = Pdip ;; No. Of Pins = 28.

N74F182D : Look-ahead Carry Generator. Provides carry look-ahead across a group of four ALUs Multi-level look-ahead for high speed arithmetic operation over The is a high speed carry look-ahead generator. It accepts up to four pairs of active-Low Carry Propagate P2, P3) and Carry Generate G2, G3) signals and an active-High Carry input (Cn) and provides anticipated active-High carries (Cn+x,.

QP1S : Cdma/amps Dual Band if Receiver For Digital Phones. CDMA/AMPS dual Band IF Receiver for Digital Phones Preliminary Information Selectable IF input buffers with characteristic impedance suitable for interface to IF CDMA and FM SAW filter outputs AGC amplifiers with 90dB of variable gain, fully compensated for temperature variation IQ demodulator with accurately defined output DC level and low DC offsets.

RF2492 : Dual-band Low Noise Amplifier/mixer. Typical Applications TDMA-GSM Cellular/PCS Handsets TDMA Cellular/PCS Handsets GAIT Handsets The is a fully featured dual-band LNA/Mixer and is usable in a variety of mobile handset applications. The unique dual IF outputs provide interface to two independent IF SAW filters supporting applications such as TDMA-EDGE where 30kHz and 200kHz bandwidth SAW filters.

SN54HC42FK : 4-line to 10-line Decoders 1 of 10. Full Decoding of Input Logic All Outputs Are High for Invalid BCD Conditions Also for Applications to 8-Line Decoders Package Options Include Plastic Small-Outline (D) and Ceramic Flat (W) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs These monolithic decimal decoders consist of eight inverters and ten 4-input.

SN75LP196DB : Low-power Multiple Rs-232 Drivers And Receivers. Single-Chip RS-232 Interface for an External Modem or Other Computer Peripheral Serial Port Designed to Transmit and Receive 4-µs Pulses (Equivalent to 256 kbit/s) Wide Driver Supply-Voltage Range: 15 V Driver Output Slew Rates Are Controlled Internally to 30 V/µs Maximum Receiver Input Hysteresis. 1000 mV Typical RS-232 Bus-Pin ESD Protection Exceeds.

TEA1085 : TEA1085; TEA1085A; Listening-in Circuit For Line-powered Telephone Sets.

0-C     D-L     M-R     S-Z