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Details, datasheet, quote on part number:GX9533
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| Part: | GX9533 |
| Category: | Interface and Interconnect => Serial Digital Interface |
| Description: | CLC018 - 8 X 8 Digital Crosspoint Switch, 1.485 Gbps, Package: Pqfp, Pin Nb=64 |
| Company: | National Semiconductor Corporation |
| Datasheet: | Download GX9533 datasheet File size : 244 kB |
| Request For quote: | Find where to buy GX9533
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Datasheet text preview:
CLC018 8 x 8 Digital Crosspoint Switch, 1.485 Gbps
July 2001
CLC018 8 x 8 Digital Crosspoint Switch, 1.485 Gbps
General Description
National's Comlinear CLC018 is a fully differential 8x8 digital crosspoint switch capable of operating at data rates exceeding 1.485 Gbps per channel. Its non-blocking architecture utilizes eight independent 8:1 multiplexers to allow each output to be independently connected to any input and any input to be connected to any or all outputs. Additionally, each output can be individually disabled and set to a highimpedance state. This TRI-STATE feature allows flexible expansion to larger switch array sizes. Low channel-to-channel crosstalk allows the CLC018 to provide superior all-hostile jitter of 50 psPP. This excellent signal fidelity along with low power consumption of 850 mW make the CLC018 ideal for digital video switching plus a variety of data communication and telecommunication applications. The fully differential signal path provides excellent noise immunity, and the I/Os support ECL and PECL logic levels. In addition, the inputs may be driven single-ended or differentially and accept a wide range of common mode levels including the positive supply. Single +5V or -5V supplies or dual +5V supplies are supported. Dual supply mode allows the control signals to be referenced to the positive supply (+5V) while the high-speed I/O remains ECL compatible. The double row latch architecture utilized in the CLC018 allows switch reprogramming to occur in the background during operation. Activation of the new configuration occurs with a single "configure" pulse. Data integrity and jitter performance on unchanged outputs are maintained during reconfiguration. Two reset modes are provided. Broadcast reset results in all outputs being connected to input port DI0. TRI-STATE Reset results in all outputs being disabled. The CLC018 is fabricated on a high-performance BiCMOS process and is available in a 64-lead plastic quad flat pack (PQFP).
Features
n Fully differential signal path n Non-Blocking n Flexible expansion to larger array sizes with very low power n Single +5/-5V or dual ± 5V operation n TRI-STATE outputs n Double row latch architecture n 64-lead PQFP package
Applications
n Serial digital video routing: SMPTE 259M for SD rates SMPTE 292M for HD rates n Telecom/datacom switching n ATM SONET
Key Specifications
n High speed: > 1.485 Gbps n Low jitter: < 50 psPP for rates < 500 Mbps < 100 ps PP for rates < 1.485 Gbps n Low power; 850 mW with all outputs active n Fast output edge speeds: 250 ps
CLC018 Block Diagram
DS100088-1
DS100088-2
© 2001 National Semiconductor Corporation
DS100088
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CLC018
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VCC V EE) VLL Maximum VLL Minimum Storage Temperature Range Lead Temp. (Soldering 4 sec.) ESD Rating Package Thermal Resistance -0.3V to +6.0V VCC +6V VCC -0.5V -65°C to +150°C +260°C TBD
JA 64-Pin PQFP JC 64-Pin PQFP Reliability Information Transistor Count
75°C/W 15°C/W 3000
Recommended Operating Conditions
Supply Voltage (VCC V Operating Temperature VLL
EE)
4.5V to 5.5V -40°C to +85°C VCC or VCC +5V
Electrical Characteristics
(VCC = 0V, VEE = -5V, VLL = 0V; unless otherwise specified) (Note 4). Parameter DYNAMIC PERFORMANCE Max. Data Rate/Channel (NRZ) Channel Jitter (Note 5) Data Rate < 500 Mbps (Note 6) Data Rate < 1.485 Gbps (Note 6) Propagation Delay (input to output) Propagation Delay Match Output Rise/Fall Time Duty Cycle Distortion CONTROL TIMING: CONFIGURATION OA Bus to LOAD Setup Time (T1) LOAD to OA Bus Hold Time (T2) IA Bus, TRI to LOAD Setup Time (T3) LOAD to IA Bus, TRI Hold Time (T4) Min Pulse Width: (T5) LOAD CNFG LOAD to CNFG Delay (T6) CNFG to Valid Delay (T 7) CNFG to Output TRI-STATE ® Delay (T8) CNFG to Output Active Delay (T9) CONTROL TIMING: RESET (Note 11) TRI to RES Setup Time (T10) RES to TRI Hold Time (T Min Pulse Width: RES (T
11) 12)
Conditions
Typ +25°C
Min/Max +25°C
Min/Max -40°C to +85°C
Units
1.485 50 100 0.75
Gbps psPP psPP ns ps ps ps ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
(Note 7) (Note 8) (Note 9)
± 200
250 10 15 0 5 5 10 10 0 20 20 70 5 5 10 20 70
RES to TRI-STATE Mode Delay (T13) RES to Broadcast Mode Delay (T14) STATIC PERFORMANCE Signal I/O: Min Input Swing, Differential Input Voltage Range Lower Limit Input Voltage Range Upper Limit Input Bias Current Output Current Output Voltage Swing (Notes 3, 12) (Note 3) RLOAD = 75 (Note 3)
150 -2 0.4 1.5 10.7 800
200
200
mVPP V V
0.4/3.1 8.53/12.80 640/960
0.3/3.8 7.20/14.3 540/1060
µA/output mA mV
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CLC018
Electrical Characteristics
Parameter STATIC PERFORMANCE Output Voltage Range Lower Limit Output Voltage Range Upper Limit Control Inputs: Input Voltage - HIGH Input Voltage - LOW Input Voltage - HIGH Input Voltage - LOW Input Current - HIGH Input Current - LOW MISCELLANEOUS PERFORMANCE VCC Supply Current VCC Supply Current VLL Supply Current VLL Supply Current Input Capacitance Output Capacitance V V V V
IH min IL max IH min IL max
(Continued)
(VCC = 0V, VEE = -5V, VLL = 0V; unless otherwise specified) (Note 4). Conditions Typ +25°C Min/Max +25°C Min/Max -40°C to +85°C Units
-2.5 0 (Note 3) (Note 3) VLL = +5V (Note 3) VLL = +5V (Note 3) VIH = VLL (Note 3) VIL = VLL -5V (Note 3) All Outputs Active (Notes 3, 13, 14) All Outputs TRI-STATE (Note 3) VLL = 0V (Note 3) VLL = +5V (Note 3) -1 -4 4 1 1 -100 -0.5 -4.5 4.5 0.5 0.2/2.0 -200/10 -0.5 -4.5 4.5 0.5 0.1/2.5 -250/15
V V V V V V µA µA
157 7 2.5 7 1.5 2
127/202 3/11 1.7/3.3
119/217 2/12 1.5/3.5
mA mA mA mA pF pF
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics" specifies conditions of device operation. Note 2: Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are determined from tested parameters. Note 3: J-level spec. is 100% tested at +25°C. Note 4: VLL and all VEE supply pins are bypassed with 0.01 µF ceramic capacitor. Note 5: Bit error rate less than 10-9 over 50% of the bit cell interval. Note 6: Measured using a pseudo-random (2 23-1 pattern) binary sequence with all other channels active with an uncorrelated signal. Note 7: Spread in propagation delays for all input/output combinations. Note 8: Measured between the 20% and 80% levels of the waveform. Note 9: Difference in propagation delay for output low-to-high vs. output high-to-low transition. Note 10: Refer to the Configuration Timing Diagram. Note 11: Refer to the Reset Timing Diagram. Note 12: The bias current for high speed data input depends on the number of data outputs that are selecting that input. Note 13: The VCC supply current is a function of the number of active data outputs. IVCC 18*N + 7 mA where N is an integer from 0 to 8. Note 14: IVEE = IVCC + I VLL.
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CLC018
Typical Performance Characteristics
DS100088-3
DS100088-4
DS100088-5
DS100088-6
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CLC018
Connection Diagram
DS100088-9
Order Number CLC018AJVJQ See NS Package Number VJQ64A
Pin Descriptions
POWER PINS VCC is the most positive rail for the data path. When the data levels are ECL compatible, then VCC should be connected to GND. For PECL data (+5V referenced ECL), VCC is connected to the +5V supply. Please refer to the device operation section in this datasheet for recommendations on the bypassing and ground/power plane requirements of this device. VEE is the most negative rail for the data path. When the data levels are ECL compatible, then VEE is connected to a -5.2V power supply. For PECL data (+5V referenced ECL), V EE is connected to GND. VLL is the logic-level power supply. If the control signals are referenced to +5V, VLL is connected to a +5V supply. If control signals are ECL compatible, VLL is connected to GND. DATA INPUT PINS DI0 and DI0 through DI7 and D17 are the data input pins to the CLC018. Depending upon how the Power pins are connected (please refer to the Power Pin section above) the data may be either differential ECL, or differential PECL. To drive the CLC018 inputs with a single-ended signal, please refer to the section "Using Single-Ended Data" in the OPERATION section of this datasheet. DATA OUTPUT PINS DO0 and DO0 through DO7 and DO7 are the data output pins of the CLC018. The CLC018 outputs are differential current outputs which can be converted to ECL or PECL compatible outputs through the use of load resistors. Please refer to the "Output Interfacing" paragraph in the OPERATION section of this datasheet for more details.
CONTROL PINS IA2, IA1 and IA0 are the three bit input selection address bus. The input port to be addressed is placed on this bus. IA2 is the Most Significant Bit (MSB). If input port 6 is to be addressed, IA2, IA1, IA0 should have 1, 1, 0 asserted on them. The IA bus should be driven with CMOS levels, if VLL is +5V. These levels are thus +5V referenced (standard CMOS). If VLL is connected to GND, the input levels are referenced to the -5V and GND supplies. OA2, OA1 and OA0 are the output selection address bus. The output port selected by the OA bus is connected to the input port selected on the IA bus when the data is loaded into the configuration registers. OA2 is the MSB. If OA2, OA1, OA0 are set to 0, 0, 1; then output port 1 will be selected. CS is an active-high chip select input. When CS is high, the RES, LOAD, and CNFG pins will be enabled. LOAD is the latch control for the LOAD register. When LOAD is high, the load register is transparent. Outputs follow the state of the IA bus, and are presented to the inputs of the Configuration register selected by the OA bus. When LOAD is low, the outputs of the Load register are latched. RES is the reset control of the configuration and load registers. A high-going pulse on the RES pin programs the switch matrix to one of two possible states: with TRI low, all outputs are connected to input #0; with TRI high, all outputs are put in TRI-STATE condition. TRI will program the selected output to be in a high impedance or TRI-STATE condition. To place an output in TRI-STATE, assert a logic-high level on the TRI input when the desired input and output addresses are asserted on the respective address inputs and strobe the LOAD input as depicted in the "Configuration Truth Table". To enable an output, assert a logic-low level on the TRI input together with the appropriate addresses and strobe the LOAD input as previously described. CNFG is the configuration register latch control. When CNFG is high the Configuration register is made transparent, and the switch matrix is set to the state loaded into the Load registers. When CNFG is low, the state of the switch matrix is latched.
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