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Details, datasheet, quote on part number:JD54174BFA
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Datasheet text preview:
54174 DM54174 DM74174 54175 DM54175 DM74175 Hex Quad D Flip-Flops with Clear
June 1989
54174 DM54174 DM74174 54175 DM54175 DM74175 Hex Quad D Flip-Flops with Clear
General Description
These positive-edge triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic All have a direct clear input and the quad (175) version features complementary I outputs from each flip-flop nformation at the D inputs meeting the setup and hold time requirements is transferred to the Q outputs on the positivegoing edge of the clock pulse Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse When the clock input is at either the high or low level the D input signal has no effect at the output C
Y Y
eatures
174 contains six flip-flops with single-rail outputs 175 contains four flip-flops with double-rail outputs Y Buffered clock and direct clear inputs Y Individual data input to each flip-flop Y Applications include B uffer storage registers Shift registers Pattern generators Y Typical clock frequency 40 MHz Y Typical power dissipation per flip-flop 38 mW F Y Alternate Military Aerospace device (54174 54175) is available Contact a National Semiconductor Sales Office Distributor for specifications
onnection Diagrams
Dual-In-Line Package Dual-In-Line Package
TL F 6557 1
TL F 6557 2
Order Number 54174DMQB 54174FMQB DM54174J D M54174W or DM74174N See NS Package Number J16A N16E or W16A
Order Number 54175DMQB 54175FMQB DM54175J D M54175W or DM74175N See NS Package Number J16A N16E or W16A
Function Table (Each Flip-Flop)
Inputs
L Clear
Outputs D X H L X Q L H L Q0 Q H L H Q0
Clock X
H H H
u u
L
H e High Level (steady state) L e Low Level (steady state) X e Don't Care
u e Transition from low to high level
Q0 e The level of Q before the indicated steady-state input conditions were established e 175 only
C1995 National Semiconductor Corporation TL F 6557 RRD-B30M105 Printed in U S A
Absolute Maximum Ratings (Note)
p If Military Aerospace specified devices are required lease contact the National Semiconductor Sales S Office Distributors for availability and specifications upply Voltage Input Voltage 7V 5 5V Note The ``Absolute Maximum Ratings'' are those values beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits The parametric values defined in the ``Electrical Characteristics'' table are not guaranteed at the absolute maximum ratings T he ``Recommended Operating Conditions'' table will define the conditions for actual device operation
Operating Free Air Temperature Range R b 55 C to a 125 C DM54 and 54 DM74 0 C to a 70 C Storage Temperature Range
b 65
C to a 150 C
ecommended Operating Conditions
Symbol VCC VIH VIL IOH IOL fCLK tW Parameter Min Supply Voltage High Level Input Voltage Low Level Input Voltage High Level Output Current Low Level Output Current Clock Frequency (Note 4) Pulse Width (Note 4) Clock Low Clock High Clear tSU tH tREL TA Data Setup Time (Note 4) Data Hold Time (Note 4) Clear Release Time (Note 4) Free Air Operating Temperature 0 25 10 20 20 0 30
b 55
DM54174 Nom 5 Max 55 Min 4 75 2 08
b0 8
DM74174 Nom 5 Max 5 25
Units V V 08
b0 8
45 2
V mA mA MHz
16 30 0 25 10 20 20 0 30 125 0
16 30
ns
ns ns ns 70
C
'174 Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted) Symbol VI VOH VOL II IIH IIL IOS ICC Parameter Input Clamp Voltage High Level Output Voltage Low Level Output Voltage Input Current Input Voltage
Max
Conditions VCC e Min II e b12 mA VCC e Min IOH e Max VIL e Max VIH e Min VCC e Min IOL e Max VIH e Min VIL e Max VCC e Max VI e 5 5V VCC e Max VI e 2 4V VCC e Max VI e 0 4V VCC e Max (Note 2) VCC e Max (Note 3) DM54 DM74
Min
Typ (Note 1)
Max
b1 5
Units V V
24 04 1 40
b1 6 b 20 b 18 b 57 b 57
V mA mA mA mA mA
High Level Input Current Low Level Input Current Short Circuit Output Current Supply Current
45
65
Note 1 All typicals are at VCC e 5V TA e 25 C Note 2 Not more than one output should be shorted at a time Note 3 With all outputs open and all DATA and CLEAR inputs at 4 5V ICC is measured after a momentary ground then 4 5V applied to the CLOCK input ote 4 TA e 25 C and VCC e 5V 2
'174 Switching Characteristics
at VCC e 5V and TA e 25 C (See Section 1 for Test Waveforms and Output Load) Symbol fMAX tPLH tPHL tPHL Parameter Maximum Clock Frequency Propagation Delay Time Low to High Level Output Propagation Delay Time High to Low Level Output Propagation Delay Time High to Low Level Output Clock to Any Q Clock to Any Q Clear to Any Q From (Input) To (Output) RL e 400X CL e 15 pF Min 30 25 25 40 Max MHz ns ns ns Units
Recommended Operating Conditions
Symbol VCC VIH VIL IOH IOL fCLK tW Parameter Min Supply Voltage High Level Input Voltage Low Level Input Voltage High Level Output Current Low Level Output Current Clock Frequency (Note 1) Pulse Width (Note 1) Clock Low Clock High Clear tSU tH tREL TA Data Setup Time (Note 1) Data Hold Time (Note 1) Clear Release Time (Note 1) Free Air Operating Temperature 0 25 10 20 20 0 30
b 55
3
DM54175 Nom 5 Max 55 Min 4 75 2 08
b0 8
DM74175 Nom 5 Max 5 25
Units V V 08
b0 8
45 2
V mA mA MHz
16 30 0 25 10 20 20 0 30 125 0
16 30
ns
ns ns ns 70
C
Note 1 TA e 25 C and VCC e 5V
'175 Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted) Symbol VI VOH VOL II IIH IIL IOS Parameter Input Clamp Voltage High Level Output Voltage Low Level Output Voltage Input Current Input Voltage
Max
Conditions VCC e Min II e b12 mA VCC e Min IOH e Max VIL e Max VIH e Min VCC e Min IOL e Max VIH e Min VIL e Max VCC e Max VI e 5 5V VCC e Max VI e 2 4V VCC e Max VI e 0 4V VCC e Max (Note 2) VCC e Max (Note 3) DM54 DM74
Min
Typ (Note 1)
Max
b1 5
Units V V
24 04 1 40
b1 6 b 20 b 18 b 57 b 57
V mA mA mA mA mA
High Level Input Current Low Level Input Current Short Circuit Output Current Supply Current
ICC
30
45
'175 Switching Characteristics
at VCC e 5V and TA e 25 C (See Section 1 for Test Waveforms and Output Load) Symbol fMAX tPLH tPHL tPLH tPHL Parameter Maximum Clock Frequency Propagation Delay Time Low to High Level Output Propagation Delay Time High to Low Level Output Propagation Delay Time Low to High Level Output Propagation Delay Time High to Low Level Output Clock to Any Q or Q Clock to Any Q or Q Clear to Any Q Clear to Any Q From (Input) To (Output) RL e 400X CL e 15 pF Min 30 25 25 25 40 Max MHz ns ns ns ns Units
Note 1 All typicals are at VCC e 5V TA e 25 C Note 2 Not more than one output should be shorted at a time ote 3 With all outputs open and 4 5V applied to all DATA and CLEAR inputs 4CC is measured after a momentary ground then 4 5V applied to the CLOCK I
Logic Diagrams
174 175
TL F 6557 4
TL F 6557 3
5
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