54F 74F161A 54F 74F163A Synchronous Presettable Binary Counter
General Description
The 'F161A and 'F163A are high-speed synchronous modulo-16 binary counters They are synchronously presettable for application in programmable dividers and have two types of Count Enable inputs plus a Terminal Count output for versatility in forming synchronous multi-stage counters The 'F161A has an asynchronous Master-Reset input that overrides all other inputs and forces the outputs LOW The 'F163A has a Synchronous Reset input that overrides counting and parallel loading and allows the outputs to be simultaneously reset on the rising edge of the clock The 'F161A and 'F163A are high-speed versions of the 'F161 and 'F163
Y Y Y Y
eatures
Synchronous counting and loading High-speed synchronous expansion Typical count frequency of 120 MHz Guaranteed 4000V minimum ESD protection
F
Commercial 74F161APC
Military
Package Number N16E
Package Description 16-Lead (0 300 Wide) Molded Dual-In-Line 16-Lead Ceramic Dual-In-Line 16-Lead (0 150 Wide) Molded Small Outline JEDEC 16-Lead (0 300 Wide) Molded Small Outline EIAJ 16-Lead Cerpack 20-Lead Ceramic Leadless Chip Carrier Type C 16-Lead (0 300 Wide) Molded Dual-In-Line 16-Lead Ceramic Dual-In-Line 16-Lead (0 150 Wide) Molded Small Outline JEDEC 16-Lead (0 300 Wide) Molded Small Outline EIAJ 16-Lead Cerpack 20-Lead Ceramic Leadless Chip Carrier Type C
Note 1 Devices also available in 13 reel Use suffix e SCX and SJX Cote 2 Military grade device with environmental and burn-in processing Use suffix e DMQB FMQB and LMQB
onnection Diagrams
Pin Assignment for DIP SOIC and Flatpak 'F161A Pin Assignment for LCC 'F161A Pin Assignment for DIP SOIC and Flatpak 'F163A Pin Assignment for LCC 'F163A
TL F 9486 1
TL F 9486 2
TL F 9486 7
TL F 9486 8
C TRI-STATE is a registered trademark of National Semiconductor Corporation 1995 National Semiconductor Corporation TL F 9486 RRD-B30M75 Printed in U S A
Logic Symbols
'F161A 'F163A
TL F 9486 3
TL F 9486 9
IEEE IEC 'F161A
IEEE IEC 'F163A
TL F 9486 6
TL F 9486 10
Unit Loading Fan Out
54F 74F Pin Names Description UL HIGH LOW 10 10 10 20 10 10 10 10 10 20 10 10 10 20 50 33 3 50 33 3 Input IIH IIL Output IOH IOL 20 mA b0 6 mA 20 mA b1 2 mA 20 mA b0 6 mA 20 mA b0 6 mA 20 mA b1 2 mA 20 mA b0 6 mA 20 mA b1 2 mA b 1 mA 20 mA b 1 mA 20 mA
CEP CET CP MR ('F161A) SR ('F163A) P0 P3 PE Q 0 Q3 TC
Functional Description
The 'F161A and 'F163A count in modulo-16 binary sequence From state 15 (HHHH) they increment to state 0 (LLLL) The clock inputs of all flip-flops are driven in parallel through a clock buffer Thus all changes of the Q outputs (except due to Master Reset of the 'F161A) occur as a result of and synchronous with the LOW-to-HIGH transition of the CP input signal The circuits have four fundamental modes of operation in order of precedence asynchronous c reset ('F161A) synchronous reset ('F163A) parallel load ' ount-up and hold Five control inputs Master Reset (MR F161A) Synchronous Reset (SR 'F163A) Parallel Enable (PE) Count Enable Parallel (CEP) and Count Enable Trickle (CET) determine the mode of operation as shown in the Mode Select Table A LOW signal on MR overrides all other inputs and asynchronously forces all outputs LOW A LOW signal on SR overrides counting and parallel loading and A allows all outputs to go LOW on the next rising edge of CP LOW signal on PE overrides counting and allows information on the Parallel Data (Pn) inputs to be loaded into the flip-flops on the next rising edge of CP With PE and MR ('F161A) or SR ('F163A) HIGH CEP and CET permit counting when both are HIGH Conversely a LOW signal on eiT ther CEP or CET inhibits counting he 'F161A and 'F163A use D-type edge triggered flip-flops and changing the SR PE CEP and CET inputs when the CP is in either state does not cause errors provided that the recommended setup and hold times with respect to the risT ing edge of CP are observed he Terminal Count (TC) output is HIGH when CET is HIGH and the counter is in state 15 To implement synchronous multi-stage counters the TC outputs can be used with the CEP and CET inputs in two different ways Please refer to the 'F568 data sheet The TC output is subject to decoding spikes due to internal race conditions and is therefore not recommended for use as a clock or asynchronous reset for L flip-flops counters or registers ogic Equations Count Enable e CEP CET PE TC e Q0 Q1 Q2 Q3 CET
State Diagram
Mode Select Table SR L H H H H PE X L H H H CET X X H L X CEP X X H X L Action on the Rising Clock Edge (L) Reset (Clear) Load (Pn x Qn) Count (Increment) No Change (Hold) No Change (Hold)
For 'F163A only H e HIGH Voltage Level L e LOW Voltage Level X e Immaterial
TL F 9486 5
3
Block Diagram
4
TL F 9486 4
Absolute Maximum Ratings (Note 1)
p If Military Aerospace specified devices are required lease contact the National Semiconductor Sales S Office Distributors for availability and specifications torage Temperature Ambient Temperature under Bias Junction Temperature under Bias Plastic VCC Pin Potential to Ground Pin Input Voltage (Note 2) Input Current (Note 2) Voltage Applied to Output in HIGH State (with VCC e 0V) Standard Output TRI-STATE Output Current Applied to Output in LOW State (Max) ESD Last Passing Voltage (Min)
ecommended Operating Conditions
Free Air Ambient Temperature Military Commercial Supply Voltage Military Commercial
b 55
C to a 150 C b 55 C to a 125 C b 55 C to a 175 C b 55 C to a 150 C
b 0 5V to a 7 0V b 0 5V to a 7 0V b 30 mA to a 5 0 mA
b 65
C to a 125 C 0 C to a 70 C
a 4 5V to a 5 5V a 4 5V to a 5 5V
b 0 5V to VCC b 0 5V to a 5 5V
twice the rated IOL (mA) 4000V
Note 1 Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired Functional operation under N these conditions is not implied ote 2 Either voltage limit or current limit is sufficient to protect inputs R
DC Electrical Characteristics
Symbol VIH VIL VCD VOH Parameter Min Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Current Input HIGH Current Breakdown Test Output HIGH Leakage Current Input Leakage Test Output Leakage Circuit Current Input LOW Current Output Short-Circuit Current Power Supply Current
b 60
54F 74F Typ Max
Units V 08
b1 2
VCC
Conditions Recognized as a HIGH Signal Recognized as a LOW Signal
IOL e 20 mA VIN e 2 7V VIN e 7 0V VOUT e VCC IID e 1 9 mA All Other Pins Grounded VIOD e 150 mV All Other Pins Grounded VIN e 0 5V (CEP CP MR P0 P3) VIN e 0 5V (CET PE SR) VOUT e 0V
