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Details, datasheet, quote on part number:JD54F373SRA
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Datasheet text preview:
54F 74F373 Octal Transparent Latch with TRI-STATE Outputs
May 1995
54F 74F373 Octal Transparent Latch with TRI-STATE Outputs
General Description
The 'F373 consists of eight latches with TRI-STATE outputs for bus organized system applications The flip-flops appear W transparent to the data when Latch Enable (LE) is HIGH hen LE is LOW the data that meets the setup times is latched Data appears on the bus when the Output Enable (OE) is LOW When OE is HIGH the bus output is in the high impedance state
Y Y Y
eatures
Eight latches in a single package TRI-STATE outputs for bus interfacing Guaranteed 4000V minimum ESD protection
F
Commercial 74F373PC
Military
Package Number N20A
Package Description 20-Lead (0 300 Wide) Molded Dual-In-Line 20-Lead Ceramic Dual-In-Line 20-Lead (0 300 Wide) Molded Small Outline JEDEC 20-Lead (0 300 Wide) Molded Small Outline EIAJ 20-Lead Molded Shrink Small Outline EIAJ Type II 20-Lead Cerpack 20-Lead Ceramic Leadless Chip Carrier Type C
54F373DM (QB) 74F373SC (Note 1) 74F373SJ (Note 1) 74F373MSA (Note 1) 54F373FM (QB) 54F373LM (QB)
J20A M20B M20D MSA20 W20A E20A
L Note 1 Devices also available in 13 reel Use suffix e SCX SJX and MSAX
ogic Symbols
IEEE IEC
Connection Diagrams
Pin Assignment for DIP SOIC SSOP and Flatpak Pin Assignment for LCC
TL F 9523 3 TL F 9523 4 TL F 9523 2
TL F 9523 1
C TRI-STATE is a registered trademark of National Semiconductor Corporation 1995 National Semiconductor Corporation TL F 9523 RRD-B30M75 Printed in U S A
Unit Loading Fan Out
54F 74F Pin Names Description UL HIGH LOW 10 10 10 10 10 10 150 40 (33 3) Input IIH IIL Output IOH IOL 20 mA b0 6 mA 20 mA b0 6 mA 20 mA b0 6 mA b 3 mA 24 mA (20 mA)
D0 D7 LE OE O0 O7
Data Inputs Latch Enable Input (Active HIGH) Output Enable Input (Active LOW) TRI-STATE Latch Outputs
Functional Description
The 'F373 contains eight D-type latches with TRI-STATE d output buffers When the Latch Enable (LE) input is HIGH ata on the Dn inputs enters the latches In this condition the latches are transparent i e a latch output will change state each time its D input changes When LE is LOW the latches store the information that was present on the D inputs a setup time preceding the HIGH-to-LOW transition of LE The TRI-STATE buffers are controlled by the Output Enable (OE) input When OE is LOW the buffers are in the bi-state mode When OE is HIGH the buffers are in the high impedance mode but this does not interfere with entering new data into the latches
ruth Table
Inputs LE H H L X OE L L L H Dn H L X X Output On H L On (no change) Z
H e HIGH Voltage Level L e LOW Voltage Level X e Immaterial Z e High Impedance State
T
Logic Diagram
TL F 9523 5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays 2
Absolute Maximum Ratings (Note 1)
p If Military Aerospace specified devices are required lease contact the National Semiconductor Sales S Office Distributors for availability and specifications torage Temperature Ambient Temperature under Bias Junction Temperature under Bias Plastic VCC Pin Potential to Ground Pin Input Voltage (Note 2) Input Current (Note 2) oltage Applied to Output in HIGH State (with VCC e 0V) Standard Output TRI-STATE Output Current Applied to Output in LOW State (Max) ESD Last Passing Voltage (Min)
b 0 5V to VCC b 0 5V to a 5 5V
C to a 150 C b 55 C to a 125 C b 55 C to a 175 C b 55 C to a 150 C
b 0 5V to a 7 0V b 0 5V to a 7 0V b 30 mA to a 5 0 mA
b 65
twice the rated IOL (mA) 4000V
Recommended Operating Conditions
Free Air Ambient Temperature Military Commercial Supply Voltage V Military Commercial
b 55
Note 1 Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired Functional operation under N these conditions is not implied ote 2 Either voltage limit or current limit is sufficient to protect inputs
C to a 125 C 0 C to a 70 C
a 4 5V to a 5 5V a 4 5V to a 5 5V
DC Electrical Characteristics
Symbol VIH VIL VCD VOH Parameter Min Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 54F 10% VCC 54F 10% VCC 74F 10% VCC 74F 10% VCC 74F 5% VCC 74F 5% VCC 54F 10% VCC 74F 10% VCC 54F 74F 54F 74F 54F 74F 74F 74F 4 75 3 75
b0 6
54F 74F Typ Max
Units V 08
b1 2
VCC
Conditions Recognized as a HIGH Signal Recognized as a LOW Signal
20
V V Min
IIN e b18 mA IOH IOH IOH IOH IOH IOH
e e e e e e b 1 mA b 3 mA b 1 mA b 3 mA b 1 mA b 3 mA
25 24 25 24 27 27 05 05 20 0 50 100 70 250 50
V
Min
VOL IIH IBVI ICEX VID IOD IIL IOZH IOZL IOS IZZ ICCZ
Output LOW Voltage Input HIGH Current Input HIGH Current Breakdown Test Output HIGH Leakage Current Input Leakage Test Output Leakage Circuit Current Input LOW Current
V mA mA mA V mA mA mA mA mA mA mA
Min Max Max Max 00 00 Max Max Max Max 0 0V Max
IOL e 20 mA IOL e 24 mA VIN e 2 7V VIN e 7 0V VOUT e VCC IID e 1 9 mA All Other Pins Grounded VIOD e 150 mV All Other Pins Grounded VIN e 0 5V VOUT e 2 7V VOUT e 0 5V VOUT e 0V VOUT e 5 25V VO e HIGH Z
Output Leakage Current Output Leakage Current Output Short-Circuit Current Bus Drainage Test Power Supply Current 38
b 60
50
b 50 b 150
500 55
3
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