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54LS109 DM54LS109A DM74LS109A Dual Positive-Edge-Triggered J-K Flip-Flops with Preset Clear and Complementary Outputs
June 1989
54LS109 DM54LS109A DM74LS109A Dual Positive-Edge-Triggered J-K Flip-Flops with Preset Clear and Complementary Outputs
General Description
This device contains two independent positive-edge-triggered J-K flip-flops with complementary outputs The J and K data is accepted by the flip-flop on the rising edge of the clock pulse The triggering occurs at a voltage level and is not directly related to the transition time of the rising edge of the clock The data on the J and K inputs may be changed while the clock is high or low as long as setup and hold times are not violated A low logic level on the preset or clear inputs will set or reset the outputs regardless of the Fgic levels of the other inputs lo
eatures
Y
Alternate Military Aerospace device (54LS109) is availD able Contact a National Semiconductor Sales Office istributor for specifications
Connection Diagram
Dual-In-Line Package
TL F 6368 1
Order D umber 54LS109DMQB 54LS109FMQB DM54LS109AJ N M54LS109AW DM74LS109AM or DM74LS109AN See NS Package Number J16A M16A N16E or W16A
Function Table
Inputs PR L H L H H H H H CLR H L L H H H H H CLK X X X J X X X L H L H X K X X X L L H H X Outputs Q H L H L Q
H e High Logic Level L e Low Logic Level X e Either Low or High Logic Level
C
u u u u
L
L H H H Toggle Q0 Q0 H L Q0 Q0
u e Rising Edge of Pulse
e This configuration is nonstable that is it will not persist when preset Q and or clear inputs return to their inactive (high) state
0 e The output logic level of Q before the indicated input conditions were T established
oggle e Each output changes to the complement of its previous level on each active transition of the clock pulse
1995 National Semiconductor Corporation
TL F 6368
RRD-B30M105 Printed in U S A
Absolute Maximum Ratings (Note)
p If Military Aerospace specified devices are required lease contact the National Semiconductor Sales S Office Distributors for availability and specifications upply Voltage Input Voltage 7V 7V Note The ``Absolute Maximum Ratings'' are those values beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits The parametric values defined in the ``Electrical Characteristics'' table are not guaranteed at the absolute maximum ratings T he ``Recommended Operating Conditions'' table will define the conditions for actual device operation
Operating Free Air Temperature Range R b 55 C to a 125 C DM54LS and 54LS DM74LS 0 C to a 70 C Storage Temperature Range
b 65
C to a 150 C
ecommended Operating Conditions
Symbol VCC VIH VIL IOH IOL fCLK fCLK tW Parameter Min Supply Voltage High Level Input Voltage Low Level Input Voltage High Level Output Current Low Level Output Current Clock Frequency (Note 2) Clock Frequency (Note 3) Pulse Width (Note 2) Clock High Preset Low Clear Low tW Pulse Width (Note 3) Clock High Preset Low Clear Low tSU Setup Time (Notes 1 2) Setup Time (Notes 1 3) Hold Time (Note 4) Free Air Operating Temperature Data High Data Low Data High Data Low 0 0 18 15 15 25 20 20 30u 20u 35u 25u 0u
b 55
DM54LS109A Nom 5 Max 55 Min 4 75 2 07
b0 4
DM74LS109A Nom 5 Max 5 25
Units V V 08
b0 4
45 2
V mA mA MHz MHz
4 25 20 0 0 18 15 15 25 20 20 30u 20u 35u 25u 0u 125 0
8 25 20
ns
ns
ns
tSU
ns ns 70
tH TA
C
Note 1 The symbol (
u) indicates the rising edge of the clock pulse is used for reference
2
Note 2 CL e 15 pF RL e 2 kX TA e 25 C and VCC e 5V Note 3 CL e 50 pF RL e 2 kX TA e 25 C and VCC e 5V ote 4 TA e 25 C and VCC e 5V
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol VI VOH VOL Parameter Input Clamp Voltage High Level Output Voltage Low Level Output Voltage Conditions VCC e Min II e b18 mA VCC e Min IOH e Max VIL e Max VIH e Min VCC e Min IOL e Max VIL e Max VIH e Min IOL e 4 mA VCC e Min II Input Current Input Voltage
Max
Min
Typ (Note 1)
Max
b1 5
Units V V
DM54 DM74 DM54 DM74 DM74 JK Clock Preset Clear
25 27
34 34 0 25 0 35 0 25 04 05 04 01 01 02 02 20 20 40 40
b0 4 b0 4 b0 8 b0 8
V
VCC e Max VI e 7V
mA
IIH
High Level Input Current
VCC e Max VI e 2 7V
JK Clock Preset Clear
mA
IIL
Low Level Input Current
VCC e Max VI e 0 4V
JK Clock Preset Clear
mA
IOS ICC
Short Circuit Output Current Supply Current
VCC e Max (Note 2) VCC e Max (Note 3)
DM54 DM74
b 20 b 20
b 100 b 100
mA mA
4
8
Switching Characteristics at VCC e 5V and TA e 25 C (See Section 1 for Test Waveforms and Output Load)
Symbol Parameter From (Input) To (Output) RL e 2 k X CL e 15 pF Min fMAX tPLH tPHL tPLH tPHL tPLH tPHL Maximum Clock Frequency Propagation Delay Time Low to High Level Output Propagation Delay Time High to Low Level Output Propagation Delay Time Low to High Level Output Propagation Delay Time High to Low Level Output Propagation Delay Time Low to High Level Output Propagation Delay Time High to Low Level Output Clock to Q or Q Clock to Q or Q Clear to Q Clear to Q Preset to Q Preset to Q 25 25 30 25 30 25 30 Max CL e 50 pF Min 20 35 35 35 35 35 35 Max MHz ns ns ns ns ns ns Units
Note 1 All typicals are at VCC e 5V TA e 25 C ote 2 Not more than one output should be shorted at a time and the duration should not exceed one second For devices with feedback from the outputs where shorting the outputs to ground may cause the outputs to change logic state an equivalent test may be performed where VO e 2 25V and 2 125V for DM54 and DM74 series respectively with the minimum and maximum limits reduced by one half from their stated values This is very useful when using automatic test N equipment ote 3 ICC is measured with all outputs open with CLOCK grounded after sett3 g the Q and Q outputs high in turn in
