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Details, datasheet, quote on part number:JM38510R75601S2A
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Datasheet text preview:
54AC273 Octal D Flip-Flop
54AC273
July 1998
54AC273 Octal D Flip-Flop
General Description
The '273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) and Master Reset (MR) input load and reset (clear) all flip-flops simultaneously. The register is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop's Q output. All outputs will be forced LOW independently of Clock or Data inputs by a LOW voltage level on the MR input. The device is useful for applications where the true output only is required and the Clock and Master Reset are common to all storage elements.
Features
n n n n n n n n n n Ideal buffer for microprocessor or memory Eight edge-triggered D flip-flops Buffered common clock Buffered, asynchronous master reset See '377 for clock enable version See '373 for transparent latch version See '374 for TRI-STATE ® version Outputs source/sink 24 mA 'ACT has TTL-compatible inputs Standard Military Drawing (SMD) -- 'AC273: 5962-87756
Logic Symbols
IEEE/IEC
DS100288-1
DS100288-2
Pin Names D0 D7 MR CP Q0 Q7
Description Data Inputs Master Reset Clock Pulse Input Data Outputs
TRI-STATE ® is a registered trademark of National Semiconductor Corporation. FACTTM is a trademark of National Semiconductor Corporation.
© 1998 National Semiconductor Corporation
DS100288
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PrintDate=1998/07/27 PrintTime=08:02:05 44014 ds100288 Rev. No. 1
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Connection Diagrams
Pin Assignment for DIP and Flatpak Pin Assignment for LCC
DS100288-3 DS100288-4
Mode Select-Function Table
Operating Mode MR Reset (Clear) Load `1' Load `0'
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial N = LOW-to-HIGH Transition
Inputs CP X
N N
Outputs Dn X H L Qn L H L
L H H
Logic Diagram
DS100288-5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VCC) DC Input Diode Current (IIK) VI = -0.5V VI = VCC + 0.5V DC Input Voltage (VI) DC Output Diode Current (IOK) VO = -0.5V VO = VCC + 0.5V DC Output Voltage (VO) DC Output Source or Sink Current (IO) DC VCC or Ground Current per Output Pin (ICC or IGND) Storage Temperature (TSTG) -0.5V to +7.0V -20 mA +20 mA -0.5V to VCC + 0.5V -20 mA +20 mA -0.5V to to VCC + 0.5V
Junction Temperature (TJ) CDIP
175°C
Recommended Operating Conditions
Supply Voltage (VCC) 'AC Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) 54AC Minimum Input Edge Rate (V/t) 'AC Devices VIN from 30% to 70% of VCC VCC @ 3.3V, 4.5V, 5.5V 2.0V to 6.0V 0V to VCC 0V to VCC -55°C to +125°C
± 50 mA ± 50 mA -65°C to +150°C
125 mV/ns
Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. National does not recommend operation of FACTTM circuits outside databook specifications.
DC Characteristics for 'AC Family Devices
Symbol Parameter VCC (V) 54AC TA = -55°C to +125°C Guaranteed Limits VIH Minimum High Level Input Voltage VIL Maximum Low Level Input Voltage VOH Minimum High Level Output Voltage 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 2.1 3.15 3.85 0.9 1.35 1.65 2.9 4.4 5.4 (Note 2) VIN = VIL or VIH IOH = -12 mA V IOH = -24 mA IOH = -24 mA IOUT = 50 µA V IOUT = -50 µA V VOUT = 0.1V or VCC - 0.1V V VOUT = 0.1V or VCC - 0.1V Units Conditions
3.0 4.5 5.5 VOL Maximum Low Level Output Voltage 3.0 4.5 5.5
2.4 3.7 4.7 0.1 0.1 0.1 V
3.0 4.5 5.5 IIN IOLD IOHD Maximum Input Leakage Current (Note 3) Minimum Dynamic Output Current 5.5 5.5 5.5
0.50 0.50 0.50 V µA mA mA
(Note 2) VIN = VIL or VIH IOL = 12 mA IOL = 24 mA IOL = 24 mA VI = VCC, GND VOLD = 1.65V Max VOHD = 3.85V Min
± 1.0
50 -50
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DC Characteristics for 'AC Family Devices
Symbol Parameter VCC (V)
(Continued)
54AC TA = -55°C to +125°C Guaranteed Limits
Units
Conditions
ICC
Maximum Quiescent Supply Current
5.5
80.0
µA
VIN = VCC or GND
Note 2: All outputs loaded; thresholds on input associated with output under test. Note 3: Maximum test duration 2.0 ms, one output loaded at a time. Note 4: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC. ICC for 54AC @ 25°C is identical to 74AC @ 25°C.
AC Electrical Characteristics
VCC Symbol Parameter (V) (Note 5) Min fmax tPLH tPHL tPHL Maximum Clock Frequency Propagation Delay Clock to Output Propagation Delay Clock to Output Propagation Delay MR to Output 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 75 90 1.0 1.0 1.0 1.0 1.0 1.0 15.0 11.0 16.0 11.5 16.0 11.5 ns ns ns 54AC TA = -55°C to +125°C CL = 50 pF Max MHz Units Fig. No.
Note 5: Voltage Range 3.3 is 3.3V ± 0.3V. Voltage Range 5.0 is 5.0V ± 0.5V
AC Operating Requirements
VCC Symbol Parameter (V) (Note 6) 54AC TA = -55°C to +125°C CL = 50 pF Guaranteed Minimum ts th tw tw trec Setup Time, HIGH or LOW Data to CP Hold Time, HIGH or LOW Data to CP Clock Pulse Width HIGH or LOW MR Pulse Width HIGH or LOW Recovery Time MR to CP 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 8.0 5.0 0 1.0 6.5 5.0 10.0 6.5 6.0 4.0 ns ns ns ns ns Units Fig. No.
Note 6: Voltage Range 3.3 is 3.3V ± 0.3V. Voltage Range 5.0 is 5.0V ± 0.5V
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Capacitance
Symbol CIN CPD Parameter Input Capacitance Power Dissipation Capacitance Typ 4.5 50.0 Units pF pF Conditions VCC = Open VCC = 5.0V
Book Extract End
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