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Details, datasheet, quote on part number:JM38510R75602SS
 
 
Part:JM38510R75602SS
Description:Octal D Flip-flop With Tri-state Outputs
Company:National Semiconductor Corporation
Datasheet:Download JM38510R75602SS datasheet   File size : 175 kB
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Datasheet text preview:
54AC374 · 54ACT374 Octal D Flip-Flop with TRI-STATE Outputs
August 1998
54AC374 · 54ACT374 Octal D Flip-Flop with TRI-STATE ® Outputs
General Description
The 'AC/'ACT374 is a high-speed, low-power octal D-type flip-flop featuring separate D-type inputs for each flip-flop and TRI-STATE outputs for bus-oriented applications. A buffered Clock (CP) and Output Enable (OE) are common to all flip-flops. Outputs source/sink 24 mA See '273 for reset version See '377 for clock enable version See '373 for transparent latch version See '574 for broadside pinout version See '564 for broadside pinout version with inverted outputs n 'ACT374 has TTL-compatible inputs n Standard Military Drawing (SMD) -- 'AC374: 5962-87694 -- 'ACT374: 5962-87631 n n n n n n
Features
n ICC and IOZ reduced by 50% n Buffered positive edge-triggered clock n TRI-STATE outputs for bus-oriented applications
Logic Symbols
IEEE/IEC
DS100289-1
DS100289-2
Pin Names D0­ D7 CP OE O0­ O7 Data Inputs
Description
Clock Pulse Input TRI-STATE Output Enable Input TRI-STATE Outputs
TRI-STATE ® is a registered trademark of National Semiconductor Corporation. FACT ® is a registered trademark of Fairchild Semiconductor Corporation.
© 1998 National Semiconductor Corporation
DS100289
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Connection Diagrams
Pin Assignment for DIP and Flatpak Pin Assignment for LCC
DS100289-4 DS100289-3
Functional Description
The 'AC/'ACT374 consists of eight edge-triggered flip-flops with individual D-type inputs and TRI-STATE true outputs. The buffered clock and buffered Output Enable are common to all flip-flops. The eight flip-flops will store the state of their individual D inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock (CP) transition. With the Output Enable (OE) LOW, the contents of the eight flip-flops are available at the outputs. When the OE is HIGH, the outputs go to the high impedance state. Operation of the OE input does not affect the state of the flip-flops.
Truth Table
Inputs Dn H L X CP
N N
Outputs OE L L H On H L Z
X
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance N = LOW-to-HIGH Transition
Logic Diagram
DS100289-5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VCC) DC Input Diode Current (IIK) VI = -0.5V VI = VCC + 0.5V DC Input Voltage (VI) DC Output Diode Current (IOK) VO = -0.5V VO = VCC + 0.5V DC Output Voltage (VO) DC Output Source or Sink Current (IO) DC VCC or Ground Current per Output Pin (ICC or IGND) Storage Temperature (TSTG) Junction Temperature (TJ) CDIP -0.5V to +7.0V -20 mA +20 mA -0.5V to VCC + 0.5V -20 mA +20 mA -0.5V to VCC + 0.5V
Recommended Operating Conditions
Supply Voltage (VCC) 'AC 'ACT Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) 54AC/ACT Minimum Input Edge Rate (V/t) 'AC Devices VIN from 30% to 70% of VCC VCC @ 3.3V, 4.5V, 5.5V Minimum Input Edge Rate (V/t) 'ACT Devices VIN from 0.8V to 2.0V VCC @ 4.5V, 5.5V 2.0V to 6.0V 4.5V to 5.5V 0V to VCC 0V to VCC -55°C to +125°C
125 mV/ns
± 50 mA ± 50 mA -65°C to +150°C
175°C
125 mV/ns
Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. National does not recommend operation of FACT ® circuits outside databook specifications.
DC Characteristics for 'AC Family Devices
Symbol VIH Parameter Minimum High Level Input Voltage VIL Maximum Low Level Input Voltage VOH Minimum High Level Output Voltage VCC (V) 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 54AC TA = -55°C to +125°C Guaranteed Limits 2.1 3.15 3.85 0.9 1.35 1.65 2.9 4.4 5.4 (Note 2) VIN = VIL or VIH 3.0 4.5 5.5 VOL Maximum Low Level Output Voltage 3.0 4.5 5.5 2.4 3.7 4.7 0.1 0.1 0.1 (Note 2) VIN = VIL or VIH 3.0 4.5 5.5 IIN IOZ Maximum Input Leakage Current Maximum TRI-STATE Current 5.5 5.5 0.50 0.50 0.50 V µA IOL VI = VCC, GND VI (OE) = VIL, VIH VI = VCC, GND VO = VCC, GND 12 mA 24 mA 24 mA V IOUT = 50 µA V IOH -12 mA -24 mA -24 mA V IOUT = -50 µA V VOUT = 0.1V or VCC - 0.1V V VOUT = 0.1V or VCC - 0.1V Units Conditions
± 1.0
± 5.0
µA
3
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