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Details, datasheet, quote on part number:JM38510R75604BR
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Datasheet text preview:
54AC574 · 54ACT574 Octal D-Type Flip-Flop with TRI-STATE Outputs
September 1998
54AC574 · 54ACT574 Octal D-Type Flip-Flop with TRI-STATE ® Outputs
General Description
The 'AC/'ACT574 is a high-speed, low power octal flip-flop with a buffered common Clock (CP) and a buffered common Output Enable (OE). The information presented to the D inputs is stored in the flip-flops on the LOW-to-HIGH Clock (CP) transition. The 'AC/'ACT574 is functionally identical to the 'AC/'ACT374 except for the pinouts.
Features
n ICC and IOZ reduced by 50% n Inputs and outputs on opposite sides of package allowing easy interface with microprocessors n Useful as input or output port for microprocessors n Functionally identical to 'AC/'ACT374 n TRI-STATE outputs for bus-oriented applications n Outputs source/sink 24 mA n 'ACT574 has TTL-compatible inputs n Standard Microcircuit Drawing (SMD) -- 'ACT574: 5962-89601
Logic Symbols
IEEE/IEC
DS100256-1
DS100256-4
Pin Names D0 D7 CP OE O0 O7 Data Inputs
Description Clock Pulse Input TRI-STATE Output Enable Input TRI-STATE Outputs
TRI-STATE ® is a registered trademark of National Semiconductor Corporation. FACTTM is a trademark of Fairchild Semiconductor Corporation.
© 1998 National Semiconductor Corporation
DS100256
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Connection Diagrams
Pin Assignment for DIP, and Flatpak Pin Assignment for LCC
DS100256-2
DS100256-3
Functional Description
The 'AC/'ACT574 consists of eight edge-triggered flip-flops with individual D-type inputs and TRI-STATE true outputs. The buffered clock and buffered Output Enable are common to all flip-flops. The eight flip-flops will store the state of their individual D inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock (CP) transition. With the Output Enable (OE) LOW, the contents of the eight flip-flops are available at the outputs. When OE is HIGH, the outputs go to the high impedance state. Operation of the OE input does not affect the state of the flip-flops.
Function Table
Inputs OE H H H H L L L L CP H H N N N N H H D L H L H L H L H Internal Outputs Q NC NC L H L H NC NC ON Z Z Z Z L H NC NC Hold Hold Load Load Data Available Data Available No Change in Data No Change in Data Function
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance N = LOW-to-HIGH Transition NC = No Change
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Logic Diagram
DS100256-5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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