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54F 74F573 Octal D-Type Latch with TRI-STATE Outputs
August 1995
54F 74F573 Octal D-Type Latch with TRI-STATE Outputs
General Description
The 'F573 is a high speed octal latch with buffered common Latch Enable (LE) and buffered common Output Enable (O T E) inputs his device is functionally identical to the 'F373 but has different pinouts
Y
eatures
Inputs and outputs on opposite sides of package allowing easy interface with microprocessors Y Useful as input or output port for microprocessors Y Functionally identical to 'F373 Y TRI-STATE outputs for bus interfacing F Y Guaranteed 4000V minimum ESD protection
Commercial 74F573PC
Military
Package Number N20A
Package Description 20-Lead (0 300 Wide) Molded Dual-In-Line 20-Lead Ceramic Dual-In-Line 20-Lead (0 300 Wide) Molded Small Outline JEDEC 20-Lead (0 300 Wide) Molded Small Outline EIAJ 20-Lead Cerpak 20-Lead Ceramic Leadless Chip Carrier Type C
54F573DM (Note 2) 74F573SC (Note 1) 74F573SJ (Note 1) 54F573FM (Note 2) 54F573LM (Note 2)
J20A M20B M20D W20A E20A
Note 1 Devices also available in 13 reel Use suffix e SCX and SJX L ote 2 Military grade device with environmental and burn-in processing Use suffix e DMQB FMQB and LMQB
ogic Symbols
Connection Diagrams
Pin Assignment for DIP SOIC and Flatpak Pin Assignment for LCC
TL F 9566 1
IEEE IEC
TL F 9566 3 TL F 9566 2
TL F 9566 4
C TRI-STATE is a registered trademark of National Semiconductor Corporation
1995 National Semiconductor Corporation
TL F 9566
RRD-B30M115 Printed in U S A
Unit Loading Fan Out
54F 74F Pin Names Description UL HIGH LOW 10 10 10 10 10 10 150 40(33 3) Input IIH IIL Output IOH IOL 20 mA b0 6 mA 20 mA b0 6 mA 20 mA b0 6 mA
b 3 mA 24 mA (20 mA)
D 0 D7 LE OE O0 O7
Data Inputs Latch Enable Input (Active HIGH) TRI-STATE Output Enable Input (Active LOW) TRI-STATE Latch Outputs
Functional Description
The 'F573 contains eight D-type latches with 3-state output buffers When the Latch Enable (LE) input is HIGH data on the Dn inputs enters the latches In this condition the latches are transparent i e a latch output will change state each time its D input changes When LE is LOW the latches store the information that was present on the D inputs a setup time preceding the HIGH-to-LOW transition of LE The 3st Wate buffers are controlled by the Output Enable (OE) input When OE is LOW the buffers are in the bi-state mode hen OE is HIGH the buffers are in the high impedance mode but this does not interfer with entering new data into the latches unction Table Inputs OE L L L H LE H H L X D H L X X Outputs O H L O0 Z
H e HIGH Voltage Level L e LOW Voltage Level F X e Immaterial O0 e Value stored from previous clock cycle
Logic Diagram
TL F 9566 5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays 2
Absolute Maximum Ratings (Note 1)
p If Military Aerospace specified devices are required lease contact the National Semiconductor Sales S Office Distributors for availability and specifications torage Temperature Ambient Temperature under Bias Junction Temperature under Bias Plastic VCC Pin Potential to Ground Pin Input Voltage (Note 2) Input Current (Note 2) Voltage Applied to Output in HIGH State (with VCC e 0V) Standard Output TRI-STATE Output Current Applied to Output in LOW State (Max) ESD Last Passing Voltage (Min)
ecommended Operating Conditions
Free Air Ambient Temperature Military Commercial Supply Voltage Military Commercial
b 55
C to a 150 C b 55 C to a 125 C b 55 C to a 175 C b 55 C to a 150 C
b 0 5V to a 7 0V b 0 5V to a 7 0V b 30 mA to a 5 0 mA
b 65
C to a 125 C 0 C to a 70 C
a 4 5V to a 5 5V a 4 5V to a 5 5V
b 0 5V to VCC b 0 5V to a 5 5V
twice the rated IOL (mA) 4000V
Note 1 Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired Functional operation under N these conditions is not implied ote 2 Either voltage limit or current limit is sufficient to protect inputs R
DC Electrical Characteristics
Symbol VIH VIL VCD VOH Parameter Min Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 54F 10% VCC 54F 10% VCC 74F 10% VCC 74F 10% VCC 74F 5% VCC 74F 5% VCC 54F 10% VCC 74F 10% VCC 54F 74F 54F 74F 54F 74F 74F 74F 4 75 3 75
b0 6
54F 74F Typ Max
Units V 08
b1 2
VCC
Conditions Recognized as a HIGH Signal Recognized as a LOW Signal
20
V V Min
IIN e b18 mA IOH IOH IOH IOH IOH IOH
e e e e e e b 1 mA b 3 mA b 1 mA b 3 mA b 1 mA b 3 mA
25 24 25 24 27 27 05 05 20 0 50 100 70 250 50
V
Min
VOL IIH IBVI ICEX VID IOD IIL IOZH IOZL IOS IZZ ICCL ICCZ
Output LOW Voltage Input HIGH Current Input HIGH Current Breakdown Test Output HIGH Leakage Current Input Leakage Test Output Leakage Circuit Current Input LOW Current
V mA mA mA V mA mA mA mA mA mA mA mA
Min Max Max Max 00 00 Max Max Max Max 0 0V Max Max
IOL e 20 mA IOL e 24 mA VIN e 2 7V VIN e 7 0V VOUT e VCC IID e 1 9 mA All Other Pins Grounded VIOD e 150 mV All Other Pins Grounded VIN e 0 5V VOUT e 2 7V VOUT e 0 5V VOUT e 0V VOUT e 5 25V VO e LOW VO e HIGH Z
Output Leakage Current Output Leakage Current Output Short-Circuit Current Bus Drainage Test Power Supply Current Power Supply Current 35 35
b 60
50
b 50 b 150
500 55 55
3
