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Details, datasheet, quote on part number:JM38510/35001B2
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Datasheet text preview:
54F 74F398 54F 74F399 Quad 2-Port Register
May 1995
54F 74F398 54F 74F399 Quad 2-Port Register
General Description
The 'F398 and 'F399 are the logical equivalents of a quad 2-input multiplexer feeding into four edge-triggered flipflops A common Select input determines which of the two 4-bit words is accepted The selected data enters the flipflops on the rising edge of the clock The 'F399 is the 16-pin version of the 'F398 with only the Q outputs of the flip-flops available
Y Y Y Y
eatures
Select inputs from two data sources Fully positive edge-triggered operation Both true and complement outputs 'F398 Guaranteed 4000V minimum ESD protection 'F399
F
Commercial 74F398PC
Military
Package Number N20A
Package Description 20-Lead (0 300 Wide) Molded Dual-In-Line 20-Lead Ceramic Dual-In-Line 20-Lead (0 300 Wide) Molded Small Outline JEDEC 20-Lead Cerpack 20-Lead Ceramic Leadless Chip Carrier Type C 20-Lead (0 300 Wide) Molded Dual-In-Line 20-Lead Ceramic Dual-In-Line 20-Lead (0 300 Wide) Molded Small Outline JEDEC 20-Lead (0 300 Wide) Molded Small Outline EIAJ 20-Lead Cerpack 20-Lead Ceramic Leadless Chip Carrier Type C
54F398DM (Note 2) 74F398SC (Note 1) 54F398FM (Note 2) 54F398LM (Note 2) 74F399PC 54F399DM (Note 2) 74F399SC (Note 1) 74F399SJ (Note 1) 54F399FM (Note 2) 54F399LM (Note 2)
J20A M20B W20A E20A N20A J20A M20B M20D W20A E20A
Note 1 Devices also available in 13 reel Use suffix e SCX and SJX C ote 2 Military grade device with environmental and burn-in processing Use suffix e DMQB FMQB and LMQB
onnection Diagrams
'F398 Pin Assignment for LCC Pin Assignment for DIP SOIC and Flatpak
TL F 9533 5 TL F 9533 6
C TRI-STATE is a registered trademark of National Semiconductor Corporation 1995 National Semiconductor Corporation TL F 9533 RRD-B30M75 Printed in U S A
Connection Diagrams (Continued)
'F399
TL F 9533 8 TL F 9533 7
Logic Symbols
'F398 IEEE IEC 'F398
TL F 9533 2
'F399
TL F 9533 1
'F399
TL F 9533 4
TL F 9533 3
Unit Loading Fan Out
54F 74F Pin Names Description UL HIGH LOW 10 10 10 10 10 10 10 10 50 33 3 50 33 3 Input IIH IIL Output IOH IOL 20 mA b0 6 mA 20 mA b0 6 mA 20 mA b0 6 mA 20 mA b0 6 mA b 1 mA 20 mA b 1 mA 20 mA
S CP I0a I0d I1a I1d Qa Qd Qa Qd
Common Select Input Clock Pulse Input (Active Rising Edge) Data Inputs from Source 0 Data Inputs from Source 1 Register True Outputs Register Complementary Outputs ('F398)
2
Functional Description
The 'F398 and 'F399 are high-speed quad 2-port registers hey select four bits of data from either of two sources (Ports) under control of a common Select input (S) The selected data is transferred to a 4-bit output register synchronous with the LOW-to-HIGH transition of the Clock input (CP) The 4-bit D-type output register is fully edge-triggered The Data inputs (I0x I1x) and Select input (S) must be stable only a setup time prior to and hold time after the LOW-to-HIGH transition of the Clock input for predictable operation The 'F398 has both Q and Q outputs Inputs S I I h h I0 I h X X
unction Table Outputs I1 X X I h Q L H L H Q H L H L
H e HIGH Voltage Level L e LOW Voltage Level F h e HIGH Voltage Level one setup time prior to the LOW-to-HIGH clock transition I e LOW Voltage Level one setup time prior to the LOW-to-HIGH clock transition X e Immaterial 'F398 only
Logic Diagram
TL F 9533 9
'F398 Only Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays 3
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