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Part: JM38510/76506B2
Category:
Description: 8-Input Universal Shift/storage Register With Common Parallel I/o Pins
Company: National Semiconductor Corporation
Datasheet: Download JM38510/76506B2 datasheet File size : 79 kB
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54ACC299 · 54ACT299 8-Input Universal Shift/Storage Register with Common Parallel I/O Pins
September 1998
54AC299 · 54ACT299 8-Input Universal Shift/Storage Register with Common Parallel I/O Pins
General Description
The 'AC/'ACT299 is an 8-bit universal shift/storage register with TRI-STATE ® outputs. Four modes of operation are possible: hold (store), shift left, shift right and load data. The parallel load inputs and flip-flop outputs are multiplexed to reduce the total number of package pins. Additional outputs are provided for flip-flops Q0, Q7 to allow easy serial cascading. A separate active LOW Master Reset is used to reset the register. n Common parallel I/O for reduced pin count n Additional serial inputs and outputs for expansion n Four operating modes: shift left, shift right, load and store n TRI-STATE outputs for bus-oriented applications n Outputs source/sink 24 mA n 'ACT299 has TTL-compatible inputs n Standard Microcircuit Drawing (SMD) 'AC299: 5962-88754 'ACT299: 5962-88771
Features
n ICC and IOZ reduced by 50%
Ordering Code: Logic Symbols
Connection Diagrams
Pin Assignment for DIP and Flatpak
DS100252-1
IEEE/IEC
DS100252-2
Pin Assignment for LCC
DS100252-3 DS100252-4
TRI-STATE ® is a registered trademark of National Semiconductor Corporation. FACT ® is a registered trademark of Fairchild Semiconductor Corporation.
© 1998 National Semiconductor Corporation
DS100252
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Connection Diagrams
Pin Names CP DS0 DS7 S0, S1 MR OE1, OE2 I/O0 I/O7 Q0, Q7
(Continued) Description
Clock Pulse Input Serial Data Input for Right Shift Serial Data Input for Left Shift Mode Select Inputs Asynchronous Master Reset TRI-STATE Output Enable Inputs Parallel Data Inputs or TRI-STATE Parallel Outputs Serial Outputs
Functional Description
The 'AC/'ACT299 contains eight edge-triggered D-type flip-flops and the interstage logic necessary to perform synchronous shift left, shift right, parallel load and hold operations. The type of operation is determined by S0 and S1, as shown in the Truth Table. All flip-flop outputs are brought out through TRI-STATE buffers to separate I/O pins that also serve as data inputs in the parallel load mode. Q0 and Q7 are also brought out on other pins for expansion in serial shifting of longer words. A LOW signal on MR overrides the Select and CP inputs and resets the flip-flops. All other state changes are initiated by the rising edge of the clock. Inputs can change when the clock is in either state provided only that the recommended setup and hold times, relative to the rising edge of CP, are observed. A HIGH signal on either OE1 or OE2 disables the TRI-STATE buffers and puts the I/O pins in the high impedance state. In this condition the shift, hold, load and reset operations can still occur. The TRI-STATE buffers are also disabled by HIGH signals on both S0 and S1 in preparation for a parallel load operation.
Truth Table
Inputs MR L H H H H S1 X H L H L S0 X H H L L CP X
N N N
Response Asynchronous Reset; Q0 Q7 = LOW Parallel Load; I/On Qn Shift Right; DS0 Q0, Q0 Q1, etc. Shift Left, DS7 Q7, Q7 Q6, etc. Hold
X
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial N = LOW-to-HIGH Transition
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2
Logic Diagram
DS100252-5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
3
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