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Details, datasheet, quote on part number:LM5025SD
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| Part: | LM5025SD |
| Category: | Power Management => PWM Controllers |
| Description: | Active Clamp Voltage Mode PWM Controller <<<>>>The LM5025 PWM Controller Contains All of The Features Necessary to Implement Power Converters Utilizing The Active Clamp / Reset Technique. The Device CAN be Configured to Control Either a P-channel Clamp Switch or an N-channel Clamp Switch. With The Active Clamp Technique, Higher Efficiencies And Greater Power Densities CAN be Realized Compared to Conventional Catch Winding or RDC Clamp / Reset Techniques. Two Control Outputs Are Provided, The Main Power Switch Control (OUT_A) And The Active Clamp Switch Control (OUT_B). The Active Clamp Output CAN be Configured For Either a Guaranteed Overlap Time (for P-channel Switch Applications) or a Guaranteed Deadtime (for N_channel Applications). The Two Internal Compound Gate Drivers Parallel Both MOS And Bipolar Devices, Providing SuperiOR GATE Drive Characteristics. This Controller is Designed For High-speed Operation Including an Oscillator Frequency Range up to 1MHz And Total PWM And Current Sense Propagation Delays Less Than 100ns. The LM5025 Includes a High-voltage Start-up Regulator That Operates Over a Wide Input Range of 13V to 90V. Additional Features Include: Line Under Voltage Lockout (UVLO), Softstart, Oscillator Up/down SYNC Capability, Precision Reference And Thermal Shutdown.<<<>>> <<<>>><<<>>>Features<<<>>>Internal Start-up Bias Regulator <<<>>>3A Compound Main Gate Driver <<<>>>Programmable Line Under-voltage Lockout (UVLO) With Adjustable Hysteresis <<<>>>Voltage Mode Control With Feed-forward <<<>>>Adjustable Dual Mode Over-current Protection <<<>>>Programmable Overlap or Deadtime Between The Main And Active Clamp Outputs <<<>>>Volt X Second Clamp <<<>>>Programmable Soft-start <<<>>>Leading Edge Blanking <<<>>>Single Resistor Programmable Oscillator <<<>>>Oscillator up / Down SYNC Capability <<<>>>Precision 5V Reference <<<>>>Thermal Shutdown |
| Company: | National Semiconductor Corporation |
| Datasheet: | Download LM5025SD datasheet File size : 324 kB |
| Request For quote: | Find where to buy LM5025SD
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Datasheet text preview:
LM5025 Active Clamp Voltage Mode PWM Controller
March 2004
LM5025 Active Clamp Voltage Mode PWM Controller
General Description
The LM5025 PWM controller contains all of the features necessary to implement power converters utilizing the Active Clamp / Reset technique. The device can be configured to control either a P-Channel clamp switch or an N-Channel clamp switch. With the active clamp technique, higher efficiencies and greater power densities can be realized compared to conventional catch winding or RDC clamp / reset techniques. Two control outputs are provided, the main power switch control (OUT_A) and the active clamp switch control (OUT_B). The active clamp output can be configured for either a guaranteed overlap time (for P-Channel switch applications) or a guaranteed deadtime (for N_Channel applications). The two internal compound gate drivers parallel both MOS and Bipolar devices, providing superior gate drive characteristics. This controller is designed for high-speed operation including an oscillator frequency range up to 1MHz and total PWM and current sense propagation delays less than 100ns. The LM5025 includes a high-voltage start-up regulator that operates over a wide input range of 13V to 90V. Additional features include: Line Under Voltage Lockout (UVLO), softstart, oscillator UP/DOWN sync capability, precision reference and thermal shutdown.
Features
n Internal Start-up Bias Regulator n 3A Compound Main Gate Driver n Programmable Line Under-Voltage Lockout (UVLO) with Adjustable Hysteresis n Voltage Mode Control with Feed-Forward n Adjustable Dual Mode Over-Current Protection n Programmable Overlap or Deadtime between the Main and Active Clamp Outputs n Volt x Second Clamp n Programmable Soft-start n Leading Edge Blanking n Single Resistor Programmable Oscillator n Oscillator UP / DOWN Sync Capability n Precision 5V Reference n Thermal Shutdown
Packages
n TSSOP-16 n LLP-16 (5x5 mm) Thermally Enhanced
Typical Application Circuit
20086901
Simplified Active Clamp Forward Power Converter
© 2004 National Semiconductor Corporation
DS200869
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LM5025
Connection Diagram
20086916
16-Lead TSSOP, LLP
Ordering Information
Order Number LM5025MTC LM5025MTCX LM5025SD LM5025SDX Package Type TSSOP-16 TSSOP-16 LLP-16 LLP-16 NSC Package Drawing MTC-16 MTC-16 SDA-16A SDA-16A Supplied As 92 Units per anti-static tube 2500 Units on Tape and Reel 1000 Units on Tape and Reel 4500 Units on Tape and Reel
Pin Description
PIN 1 2 NAME VIN RAMP DESCRIPTION Source Input Voltage Modulator ramp signal APPLICATION INFORMATION Input to start-up regulator. Input range 13V to 90V, with transient capability to 100V. An external RC circuit from Vin sets the ramp slope. This pin is discharged at the conclusion of every cycle by an internal FET, initiated by either the internal clock or the V*Sec Clamp comparator.
3
CS1
Current sense input for cycle-by-cycle limiting If CS1 exceeds 0.25V the outputs will go into Cycle-by-Cycle current limit. CS1 is held low for 50ns after OUT_A switches high providing leading edge blanking. Current sense input for soft restart If CS2 exceeds 0.25V the outputs will be disabled and a softstart commenced. The soft-start capacitor will be fully discharged and then released with a pull-up current of 1µA. After the first output pulse (when SS =1V), the SS charge current will revert back to 20µA. CS2 is held low for 50ns after OUT_A switches high, providing leading edge blanking. An external resistor (RSET) sets either the overlap time or dead time for the active clamp output. An RSET resistor connected between TIME and GND produces in-phase OUT_A and OUT_B pulses with overlap. An RSET resistor connected between TIME and REF produces out-of-phase OUT_A and OUT_B pulses with deadtime. Maximum output current: 10mA Locally decouple with a 0.1µF capacitor. Reference stays low until the line UVLO and the VCC UV comparators are satisfied.
4
CS2
5
TIME
Output overlap/Deadtime control
6
REF
Precision 5 volt reference output
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2
LM5025
Pin Description
PIN 7 NAME VCC
(Continued) DESCRIPTION APPLICATION INFORMATION
Output from the internal high voltage start-up If an auxiliary winding raises the voltage on this pin above the regulation setpoint, the internal start-up regulator. The VCC voltage is regulated to 7.6V. regulator will shutdown, reducing the IC power dissipation. Main output driver Active Clamp output driver Power ground Analog ground Output of the main switch PWM output gate driver. Output capability of 3A peak sink current. Output of the Active Clamp switch gate driver. Capable of 1.25A peak sink current.. Connect directly to analog ground. Connect directly to power ground. For the LLP package option the exposed pad is electrically connected to AGND. An external capacitor and an internal 20µA current source set the softstart ramp. The SS current source is reduced to 1uA initially following a CS2 over-current event or an over temperature event. An internal 5K resistor pull-up is provided on this pin. The external opto-coupler sinks current from COMP to control the PWM duty cycle. An external resistor connected from RT to ground sets the internal oscillator frequency. The internal oscillator can be synchronized to an external clock with a frequency 20% lower than the internal oscillator's free running frequency. There is no constraint on the maximum sync frequency. An external voltage divider from the power source sets the shutdown comparator levels. The comparator threshold is 2.5V. Hysteresis is set by an internal current source (20µA) that is switched on or off as the UVLO pin potential crosses the 2.5V threshold.
8 9 10 11
OUT_A OUT_B PGND AGND
12
SS
Soft-start control
13
COMP
Input to the Pulse Width Modulator
14 15
RT SYNC
Oscillator timing resistor pin Oscillator UP/DOWN synchronization input
16
UVLO
Line Under-Voltage shutdown
3
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