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Details, datasheet, quote on part number:LM5642
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| Part: | LM5642 |
| Category: | Power Management => Regulators => Switching Regulators |
| Description: | LM5642 - High Voltage, Dual Synchronous Buck Converter With Oscillator Synchronization, Package: Evaluation Board, Pin Nb=- |
| Company: | National Semiconductor Corporation |
| Datasheet: | Download LM5642 datasheet File size : 683 kB |
| Request For quote: | Find where to buy LM5642
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Datasheet text preview:
LM5642 High Voltage, Dual Synchronous Buck Converter with Oscillator Synchronization
June 2003
LM5642 High Voltage, Dual Synchronous Buck Converter with Oscillator Synchronization
General Description
The LM5642 consists of two current mode synchronous buck regulator controllers operating 180° out of phase with each other at a normal switching frequency of 200kHz. Out of phase operation reduces the input ripple RMS current, thereby significantly reducing the required input capacitance. The switching frequency can be synchronized to an external clock between 150kHz and 250kHz. The two switching regulator outputs can also be paralleled to operate as a dual-phase single output regulator. The output of each channel can be independently adjusted from 1.3 to 90% of Vin. An internal 5V rail is also available externally for driving bootstrap circuitry. Current-mode feedback control assures excellent line and load regulation and a wide loop bandwidth for excellent response to fast load transients. Current is sensed across either the Vds of the top FET or across an external currentsense resistor connected in series with the drain of the top FET. The LM5642 features analog soft-start circuitry that is independent of the output load and output capacitance making the soft-start behavior more predictable and controllable than traditional soft-start circuits. Over-voltage protection is available for both outputs. A UVDelay pin is also available to allow delayed shut off time for the IC during an output under-voltage event.
Features
n Two synchronous buck regulators n 180° out of phase operation n Synchronizable switching frequency from 150kHz to 250kHz n 4.5V to 36V input range n 50µA Shutdown current n Adjustable output from 1.3V to 90% of Vin n 0.04% (typical) line and load regulation error n Current mode control with or without a sense resistor n Independent enable/soft-start pins allow simple sequential startup configuration. n Configurable for single output parallel operation. (See Figure 2) n Adjustable cycle-by-cycle current limit n Input under-voltage lockout n Output over-voltage latch protection n Output under-voltage protection with delay n Thermal shutdown n Self discharge of output capacitors when the regulator is OFF n TSSOP package
Applications
n n n n n Embedded Computer Systems Telecom Systems Set-Top Boxes WebPAD Point Of Load Power Architectures
Typical Application Circuit
20060101
© 2003 National Semiconductor Corporation
DS200601
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LM5642
Connection Diagram
TOP VIEW
20060102
28-Lead TSSOP (MTC) Order Number LM5642MTC See NS Package Number MTC28
Pin Descriptions
KS1 (Pin 1): The positive (+) Kelvin sense for the internal current sense amplifier of Channel 1. Use a separate trace to connect this pin to the current sense point. It should be connected to VIN as close as possible to the node of the current sense resistor. When no current-sense resistor is used, connect as close as possible to the drain node of the upper MOSFET. ILIM1 (Pin 2): Current limit threshold setting for Channel 1. It sinks a constant current of 9.9µA, which is converted to a voltage across a resistor connected from this pin to VIN. The voltage across the resistor is compared with either the VDS of the top MOSFET or the voltage across the external current sense resistor to determine if an over-current condition has occurred in Channel 1. COMP1 (Pin 3): Compensation pin for Channel 1. This is the output of the internal transconductance amplifier. The compensation network should be connected between this pin and the signal ground, SGND (Pin 8). FB1 (Pin 4): Feedback input for channel 1. Connect to VOUT through a voltage divider to set the Channel 1 output voltage. SYNC (Pin 5): The switching frequency of the LM5642 can be synchronized to an external clock. SYNC = LOW: Free running at 200kHz, channels are 180° out of phase. SYNC = HIGH: Waiting for external clock SYNC = Falling Edge: Channel 1 HDRV pin goes high. Channel 2 HDRV pin goes high after 2.5µs delay. The maximum SYNC pulse width must be greater than 100ns. For SYNC = Low operation, connect this pin to signal ground through a 220k resistor. UV_DELAY (Pin 6): A capacitor from this pin to ground sets the delay time for UVP. The capacitor is charged from a 5µA
current source. When UV_DELAY charges to 2.3V (typical), the system immediately latches off. Connecting this pin to ground will disable the output under-voltage protection. VLIN5 (Pin 7): The output of an internal 5V LDO regulator derived from VIN. It supplies the internal bias for the chip and supplies the bootstrap circuitry for gate drive. Bypass this pin to signal ground with a minimum of 4.7µF ceramic capacitor. SGND (Pin 8): The ground connection for the signal-level circuitry. It should be connected to the ground rail of the system. ON/SS1 (Pin 9): Channel 1 enable pin. This pin is internally pulled up to one diode drop above VLIN5. Pulling this pin below 1.2V (open-collector type) turns off Channel 1. If both ON/SS1 and ON/SS2 pins are pulled below 1.2V, the whole chip goes into shut down mode. Adding a capacitor to this pin provides a soft-start feature that minimizes inrush current and output voltage overshoot. ON/SS2 (Pin 10): Channel 2 enable pin. See the description for Pin 9, ON/SS1. May be connected to ON/SS1 for simultaneous startup or for parallel operation. FB2 (Pin 11): Feedback input for channel 2. Connect to VOUT through a voltage divider to set the Channel 2 output voltage. COMP2 (Pin 12): Compensation pin for Channel 2. This is the output of the internal transconductance amplifier. The compensation network should be connected between this pin and the signal ground SGND (Pin 8). ILIM2 (Pin 13): Current limit threshold setting for Channel 2. See ILIM1 (Pin 2). KS2 (Pin 14): The positive (+) Kelvin sense for the internal current sense amplifier of Channel 2. See KS1 (Pin 1). RSNS2 (Pin 15): The negative (-) Kelvin sense for the internal current sense amplifier of Channel 2. Connect this pin to the low side of the current sense resistor that is placed between VIN and the drain of the top MOSFET. When the
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LM5642
Pin Descriptions
(Continued)
LDRV2 (Pin 20): Low-side gate-drive output for Channel 2. PGND (Pin 21): The power ground connection for both channels. Connect to the ground rail of the system. VIN (Pin 22): The power input pin for the chip. Connect to the positive (+) input rail of the system. This pin must be connected to the same voltage rail as the top FET drain (or the current sense resistor when used). LDRV1 (Pin 23): Low-side gate-drive output for Channel 1. VDD1 (Pin 24): The supply rail for Channel 1 low-side gate drive. Tie this pin to VDD2 (Pin 19). CBOOT1 (Pin 25): : Bootstrap capacitor connection. It serves as the positive supply rail for Channel 1 top-side gate drive. See CBOOT2 (Pin 18). HDRV1 (Pin 26): Top-side gate-drive output for Channel 1. See HDRV2 (Pin 17). SW1 (Pin 27): Switch-node connection for Channel 1. See SW2 (Pin16). RSNS1 (Pin 28): The negative (-) Kelvin sense for the internal current sense amplifier of Channel 1. See RSNS2 (Pin 15).
Rds of the top MOSFET is used for current sensing, connect this pin to the source of the top MOSFET. Always use a separate trace to form a Kelvin connection to this pin. SW2 (Pin 16): Switch-node connection for Channel 2, which is connected to the source of the top MOSFET of Channel 2. It serves as the negative supply rail for the top-side gate driver, HDRV2. HDRV2 (Pin 17): Top-side gate-drive output for Channel 2. HDRV is a floating drive output that rides on the corresponding switching-node voltage. CBOOT2 (Pin 18): Bootstrap capacitor connection. It serves as the positive supply rail for the Channel 2 top-side gate drive. Connect this pin to VDD2 (Pin 19) through a diode, and connect the low side of the bootstrap capacitor to SW2 (Pin16). VDD2 (Pin 19): The supply rail for the Channel 2 low-side gate drive. Connected to VLIN5 (Pin 7) through a 4.7 resistor and bypassed to power ground with a ceramic capacitor of at least 1µF. Tie this pin to VDD1 (Pin 24).
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