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Details, datasheet, quote on part number:LMC568CN
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| Part: | LMC568CN |
| Category: | Timing Circuits => Timers => Timers and Oscillators |
| Description: | LMC568 - Low Power Phase-locked Loop, Package: Soic Narrow, Pin Nb=8 |
| Company: | National Semiconductor Corporation |
| Datasheet: | Download LMC568CN datasheet File size : 165 kB |
| Request For quote: | Find where to buy LMC568CN
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Datasheet text preview:
LMC568 Low Power Phase-Locked Loop
May 1999
LMC568 Low Power Phase-Locked Loop
General Description
The LMC568 is an amplitude-linear phase-locked loop consisting of a linear VCO, fully balanced phase detectors, and a carrier detect output. LMCMOSTM technology is employed for high performance with low power consumption. The VCO has a linearized control range of ± 30% to allow demodulation of FM and FSK signals. Carrier detect is indicated when the PLL is locked to an input signal greater than 26 mVrms. LMC568 applications include FM SCA and TV second audio program decoders, FSK data demodulators, and voice pagers.
Features
n n n n n n Demodulates ± 15% deviation FM/FSK signals Carrier Detect Output with hysteresis Operation to 500 kHz input frequency Low THD -- 0.5% typ. for ± 10% deviation 2V to 9V supply voltage range Low supply current drain
Typical Application
(100 kHz input frequency, refer to notes pg. 3)
DS009135-1
Order Number LMC568CM or LMC568CN See NS Package Number M08A or N08E
LMCMOSTM is a trademark of National Semiconductor Corporation.
© 1999 National Semiconductor Corporation
DS009135
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Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Input Voltage, Pin 3 Supply Voltage, Pin 4 Output Voltage, Pin 8 Voltage at All Other Pins Output Current, Pin 8 Package Dissipation Operating Temperature Range (TA) Storage Temperature Range 2 Vp p 10V 13V Vs to Gnd 30 mA 500 mW -25°C to +125°C -55°C to +150°C
Soldering Information Dual-In-Line Package Soldering (10 seconds) 260°C Small Outline Package Vapor Phase (60 seconds) 215°C Infrared (15 seconds) 220°C See AN-450 "Surface Mounting Methods and their Effect on Product Reliability" for other methods of soldering surface mount devices.
Note 1: "Absolute Maximum Ratings" indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits.
Electrical Characteristics
Test Circuit, TA = 25°C, VS = 5V, RtCt #2, Sw. 1 Pos. 0; and no input unless otherwise noted. Symbol I4 Parameter Power Supply Current Conditions RtCt # 1, Quiescent or Activated VS = 2V VS = 5V VS = 9V V3 R3 I8 f0 Input D.C. Bias Input Resistance Output Leakage Center Frequency Fosc ÷2 Center Frequency Shift with Supply Input Threshold Set Input Frequency Equal to f0 Measured Above, Increase Input Level until Pin 8 Goes Low. VS = 2V VS = 5V VS = 9V 8 15 RtCt #2, Measure Oscillator Frequency and Divide by 2 VS = 2V VS = 5V VS = 9V f 0 90 Min Typ 0.35 0.75 1.2 0 40 1 98 103 105 1.0 16 26 45 1.5 0.06 0.7 30 40 55 60 % 0.15 mVrms Vdc 2.0 25 42 mVrms %/V 115 kHz 100 1.5 2.4 mVdc k nAdc mAdc Max Units
Vin
Vin V8
Input Hysteresis Output Sat Voltage
Starting at Input Threshold, Decrease Input Level until Pin 8 Goes High Input Level > Threshold Choose RL for Specified I8 Measure Fosc with Sw. 1 in Pos. 0, 1, and 2; I8 = 2 mA I8 = 20 mA VS = 2V VS = 5V VS = 9V
L.D.B.W. Largest Detection Bandwidth
BW
Bandwidth Skew 1
±5
%
Vout
Recovered Audio
Typical Application Circuit Input = 100 mVrms, F = 100 kHz Fmod = 400 Hz, ± 10 kHz Dev.
VS = 2V VS = 5V VS = 9V
170 270 400 0.5 % mVrms
THD
Total Harmonic Distortion Signal to Noise Ratio
Typical Application Circuit as Above, Measure Vout Distortion. Typical Application Circuit Remove Modulation, Measure Vn (S + N)/N = 20 log (Vout/Vn). RtCt #3, Measure Oscillator Frequency and Divide by 2
65
dB
fmax
Highest Center Freq.
700
kHz
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2
Test Circuit
DS009135-3
RtCt
Rt 100k 10k 5.1k
Ct 300 pF 300 pF 62 pF OUTPUT TAKEOFF The output signal is taken off the loop filter at pin 2. Pin 2 is the combined output of the phase detector and control input of the VCO for the phase-locked loop (PLL). The nominal pin 2 source resistance is 80 k, requiring the use of an external buffer transistor to drive nominal loads. For small values of C2, the PLL will have a fast acquisition time and the pull-in range will be set by the built-in VCO frequency stops, which also determine the largest detection bandwidth (LDBW). Increasing C2 results in improved noise immunity at the expense of acquisition time, and the pull-in range will become narrower than the LDBW. However, the maximum hold-in range will always equal the LDBW. The 2 kHz de-emphasis pole shown may be modified or omitted as required by the application. CARRIER DETECT Pin 1 is the output of a negative-going amplitude detector which has a nominal 0 signal output of 7/9 Vs. The output at pin 8 is an N-channel FET switch to ground which is activated when the PLL is locked and the input is of sufficient amplitude to cause pin 1 to fall below 2/3 Vs. The carrier detect threshold is internally set to 26 mVrms typical on a 5V supply. Capacitor C1 in conjunction with the nominal 40 k pin 1 internal resistance forms the output filter. The size of C1 is a tradeoff between slew rate and carrier ripple at the output comparator. Optional resistor RH increases the hysteresis in the pin 8 output for applications such as audio mute control. The minimum allowable value for RH is 330 k.
#1 #2 #3
Notes to Typical Application
SUPPLY DECOUPLING The decoupling of supply pin 4 becomes more critical at high supply voltages with high operating frequencies, requiring C4 to be placed as close to possible to pin 4. Also, due to pin voltages tracking supply, a large C4 is necessary for low frequency PSRR. OSCILLATOR TIMING COMPONENTS The voltage-controlled oscillator (VCO) on the LMC568 must be set up to run at twice the frequency of the input signal. The components shown in the typical application are for Fosc = 200 kHz (100 kHz input frequency). For operation at lower frequencies, increase the capacitor value; for higher frequencies proportionally reduce the resistor values. If low distortion is not a requirement, the series diode/resistor between pins 6 and 5 may be omitted. This will reduce VCO supply dependence and increase Vout by approximately 2 dB with THD = 2% typical. The center frequency as a function of Rt and Ct is given by:
To allow for I.C. and component value tolerences, the oscillator timing components will require a trim. This is generally accomplished by using a variable resistor as part of Rt, although Ct could also be padded. The amount of initial frequency variation due to the LMC568 itself is given in the electrical specifications; the total trim range must also accommodate the tolerances of Rt and Ct. INPUT PIN The input pin 3 is internally ground-referenced with a nominal 40 k resistor. Signals that are centered on 0V may be directly coupled to pin 3; however, any d.c. potential must be isolated via C3.
3
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