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Details, datasheet, quote on part number:LMX5001VBC
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Datasheet text preview:
LMX5001 Dedicated Bluetooth Link Controller
PRELIMINARY
April 2000
LMX5001 Dedicated Bluetooth Link Controller
General Description
The LMX5001 Dedicated BluetoothTM Link Controller has been designed to interface with the LMX3162, Single Chip Radio Transceiver to provide a rapid design path to a complete Bluetooth physical layer. The LMX5001 also offers a low power and cost competitive solution to the Bluetooth Link Controller function. The LMX5001 can be attached to a Link Management Controller, or Host processor performing the Link Management function to implement a complete Bluetooth interface. Bluetooth is a world-wide recognized wireless communication standard, which operates in the ISM band (2.4 GHz), offering a low cost and convenient wireless replacement for data/voice cable links between fixed and mobile electronic devices. Utilizing a GFSK modulation scheme, with frequency hopping, Bluetooth is able to offer a low power, low cost, robust and spectrally efficient spread spectrum packet data system. n Piconet and Scatternet communication capable n Good Bluetooth radio range coverage (when coupled with the LMX3162) n Support for RSSI channel quality monitoring n Bluetooth Encryption Engine
Applications
n n n n n n n n n n n n n n n n n PCMCIA Cards Mobile Phones Laptop PCs Palmtop PCs Desktop PCs Computer Peripherals Wireless Modems PDAs Palmtops P.O.T.S Digital Cameras Fax Printers Bar-code Readers Notepads Cordless Headsets In-vehicle Communications
Features
n Bluetooth Specification 1.0B compliant n Bluetooth physical layer, available today n Supports Class 1, 2 and 3 Bluetooth (20 dBm, 4 dBm and 0 dBm links) n 1/8 bit sampling resolution n Power management for Tx, Rx and PLL
Block Diagram
Functional Block Diagram
DS101340-1
© 2000 National Semiconductor Corporation
DS101340
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LMX5001
Connection Diagram
DS101340-7
Pin Descriptions
Pin No. 1 2 3 4 Pin Name BT_TxData VCO_BS S_FIELD2 S_FIELD1 I/O O O O O Transmit data VCO band switch control signal. LMX3162 DC compensation circuit enable. This signal is enabled (low) throughout the correlation phase. LMX3162 DC compensation circuit enable. At the beginning of the correlation phase this signal is enabled (low) for 15 µs. For the remainder of the correlation phase this signal is PWM by 1/8 (cycle time = 1 µs). LMX3162 4 MHz oscillator input to the PLL synthesizer. This signal is only enabled when the LMX3162 is active. MICROWIRETM data to LMX3162. MICROWIRE load enable to LMX3162. MICROWIRE clock to LMX3162. LMX3162 PLL power down. This signal is used to open the PLL loop or powering down the PLL. The PLL loop is opened when transmitting to make it possible to FSK modulate the VCO. When receiving it is optional to open the PLL loop (configured by the PLLOpenRX bit in threshold_msb). LMX3162 Transmitter power down. For power conservation, the Transmitter is only powered during Transmit Frames. LMX3162 Receiver power down. For power conservation, the Receiver is only powered during Receive Frames. LMX3162 chip enable. When the LMX5001 is in Idle Mode the LMX3162 is powered down. +3.3V 0V Antenna switch control. Antenna switch control. This signal is RFSW1 inverted, Switches the external PA on/off for 20 dBm/0 dBm transmission, respectively.
2
Description
5 6 7 8 9
R_OSC R_DATA R_LE R_CLK PLL_PD
O O O O O
10 11 12 13 14 15 16 17
Tx_PD Rx_PD R_CE VCC GND RFSW1 RFSW2 PA_ON
O O O Power Power O O O
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LMX5001
Pin Descriptions
Pin No. 18 19 20 Pin Name GPIO0 (XTAL Config) GPIO1 (XTAL Config) LPXTALI
(Continued) I/O I/O I/O I Description XTAL configuration during reset (Note 1). XTAL configuration during reset (Note 1). 128 kHz XTAL connection for low power mode. This is used in low power mode. If the low power mode is not used it is not necessary with at XTAL here. External 128 kHz clock can also be feed in here. 128 kHz XTAL connection. General Purpose I/O General Purpose I/O General Purpose I/O LCI Data Transmit LCI Data Receive LCI Receive Frame Sync. LCI Transmit Frame Sync. LCI Serial Clock. Power Down to Link Management Controller Power Down Acknowledge from Link Management Controller PWM signal to make adjustments to the XTAL. 16 MHz XTAL connection. (External clock input). 16 MHz XTAL connection. Systick generated from the internal LMX5001 Master/Slave Counter. When low holds the LMX5001 in Idle Mode. A rising edge causes a system load After a rising edge the LMX5001 will start to load control data from and store status information to the LMC via the LCI.
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
LPXTALO GPIO2 GPIO3 GPIO4 TxData RxData RxFrSync TrFrSync SCLK PWDN PWDNACK Xtal_adj XTALI XTALO SYSTICK SYSLOAD
O I/O I/O I/O I O O O O O I O I O O I
37 38 39 40 41 42 43 44 45 46 47 48
VCC GND Reset Test0 Test1 CLKOUT GPIO5 Q_adj RSSI_adj COMP_RSSI S_Field3 BT_RxData
Power Power I I I O I/O O O I O I Reset. After Reset is released the LMX5001 will be in Idle Mode, awaiting a SYSLOAD. Should be tied low. This signal is used in production test. Should be lied low. This signal is used in production test. Xtal clock output to Link Management Controller. This signal can be disabled using the Sysload Command (for power saving). General Purpose I/O PWM signal to make it possible to adjust the quadrature tank circuit to the LMX3162. PWM signal for use in creating an RSSI AD converter. Output from the external comparator in the RSSI AD converter. DC Compensation circuit enable. At the beginning of the correlation phase, this signal is enabled (low) for 15 µs. Receive data.
Note 1: During Reset GPIO0 and GPIO1 are sampled to setup the Xtal division ratio. The assumed external Xtal frequency is derived using the following relationship:
GPIO1 Low Low High High
GPIO0 Low High Low High
Xtal Division Ratio Divide by 2 (i.e., 16 MHz XTAL or clock input). Divide by 3 (i.e., 24 MHz XTAL or clock input). Divide by 4 (i.e., 32 MHz XTAL or clock input). Not used.
After Reset is completed, GPIO0 and GPIO1 can be used as normal general purpose I/Os.
3
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