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Part: MF4C-50
Category:
Analog & Mixed-Signal Processing
-> Filters
-> Low Pass Filters
Description: 4th Order Switched Capacitor Butterworth Lowpass Filter (life-time Buy)
Company: National Semiconductor Corporation
Datasheet: Download MF4C-50 datasheet File size : 700 kB
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Datasheet text preview:
MF4 4th Order Switched Capacitor Butterworth Lowpass Filter
July 1999
MF4 4th Order Switched Capacitor Butterworth Lowpass Filter
General Description
The MF4 is a versatile, easy to use, precision 4th order Butterworth low-pass filter. Switched-capacitor techniques eliminate external component requirements and allow a clock-tunable cutoff frequency. The ratio of the clock frequency to the low-pass cutoff frequency is internally set to 50 to 1. A Schmitt trigger clock input stage allows two clocking options, either self-clocking (via an external resistor and capacitor) for stand-alone applications, or for tighter cutoff frequency control an external TTL or CMOS logic compatible clock can be applied. The maximally flat passband frequency response together with a DC gain of 1 V/V allows cascading MF4 sections together for higher order filtering.
Features
n n n n n n n n n Low Cost Easy to use 8-pin mini-DIP or 14-pin wide-body S.O. No external components 5V to 14V supply voltage Cutoff frequency range of 0.1 Hz to 20 kHz Cutoff frequency accuracy of ± 0.3% typical Cutoff frequency set by external clock Separate TTL and CMOS/Schmitt-trigger clock inputs
Connection Diagram
Dual-In-Line Package
DS005064-2
Order Number MF4CN-50 See NS Package Number N08E
Block Diagram
DS005064-1
TRI-STATE ® is a registered trademark of National Semiconductor Corp.
© 1999 National Semiconductor Corporation
DS005064
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Block Diagram
Pin Pin Name CLK IN
(Continued)
Pin
Pin Name FILTER IN
Function The input to the low-pass filter. To minimize gain errors the source impedance that drives this input should be less than 2K (see section 1.3 of the Application Hints). For single supply operation the input signal must be biased to mid-supply or AC coupled through a capacitor.
Pin Descriptions
Function A CMOS Schmitt-trigger input to be used with an external CMOS logic level clock. Also used for self clocking Schmitt-trigger oscillator (see section 1.1). A TTL logic level clock input when in split supply operation ( ± 2.5V to ± 7V) with L. Sh tied to system ground. This pin becomes a low impedance output when L. Sh is tied to V-. Also used in conjunction with the CLK IN pin for a self clocking Schmitt-trigger oscillator (see section 1.1). The TTL input signal must not exceed the supply voltages by more than 0.2V. Level shift pin; selects the logic threshold levels for the clock. When tied to V- it enables an internal tri-state buffer stage between the Schmitt trigger and the internal clock level shift stage thus enabling the CLK IN Schmitt-trigger input and making the CLK R pin a low impedance output. When the voltage level at this input exceeds 25% (V+ - V-) + V- the internal tri-state buffer is disabled allowing the CLK R pin to become the clock input for the internal clock level-shift stage. The CLK R threshold level is now 2V above the voltage on the L. Sh pin. The CLK R pin will be compatible with TTL logic levels when the MF4 is operated on split supplies with the L. Sh pin connected to system ground. The output of the low-pass filter. It will typically sink 0.9 mA and source 3 mA and swing to within 1V of each supply rail. The analog ground pin. This pin sets the DC bias level for the filter section and must be tied to the system ground for split supply operation or to mid-supply for single supply operation (see section 1.2). When tied to mid-supply this pin should be well bypassed. The positive and negative supply pins. The total power supply range is 5V to 14V. Decoupling these pins with 0.1 µF capacitors is highly recommended.
#
8
#
1
2
CLK R
3
L. Sh
5
FILTER OUT
6
AGND
7, 4
V+, V-
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2
Absolute Maximum Ratings (Notes 1, 2)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (V+ V-) Voltage At Any Pin Input Current at Any Pin (Note 14) Package Input Current (Note 14) Power Dissipation (Note 15) 14V V+ + 0.2V V- - 0.2V 5 mA 20 mA 500 mW
Storage Temperature ESD Susceptibility (Note 13) Soldering Information (10 sec.)
150°C 800 V 260°C (Note 2) Tmin TA Tmax 0°C TA 70°C 5V to 14V
Operating Ratings
Temperature Range MF4CN-50 Supply Voltage (V+ V-)
Filter Electrical Characteristics
The following specifications apply for fCLK 250 kHz (Note 5) unless otherwise specified. Boldface limits apply for TMIN to TMAX; all other limits TA = TJ = 25°C.
Parameter Conditions Typical (Note 10) V+ = +5V, V- = -5V fc, Cutoff Frequency Range (Note 3) Supply Current Maximum Clock Feedthrough (Peak-to-Peak) Ho, DC Gain fclk/fc, Clock to Cutoff Frequency Ratio fclk/fc Temperature Coefficient Stopband Attenuation (Min) DC Offset Voltage Minimum Output Swing Output Short Circuit Current (Note 8) Dynamic Range (Note 4) Additional Magnitude Response Test Points (Note 6) fclk = 250 kHz f = 3000 Hz dB f = 2250 Hz V+ = +2.5V, V- = -2.5V fc Cutoff Frequency Range (Note 3) Supply Current Maximum Clock Feedthrough (Peak-to-Peak) Ho, DC Gain fclk/fc, Clock to Cutoff Frequency Ratio fCLK/fC Temperature Coefficient Rsource 2 k 0.0 50.07 Filter Output Vin = 0V 15 mV min max fclk = 250 kHz 1.5 2.25 0.1 10k 2.25 mA Hz f = 4500 Hz f = 6000 Hz Source Sink RL = 10 k at 2 fc -25.0 -200 +4.0 -4.5 50 1.5 80 -7.57 -7.57 +3.5 -4.0 +3.5 -4.0 -24.0 -24.0 dB mV V V mA mA dB Rsource 2 k 0.0 49.96 Filter Output Min Max fclk = 250 kHz Vin = 0V 25 mV 2.5 3.5 0.1 20k 3.5 mA Hz Tested Limit (Note 11) Design Limit (Note 12) Unit
± 0.15
49.96
± 0.15
dB
± 0.3% ± 15
± 1%
ppm/°C
± 0.47
-1.44
± 0.47
-1.44
dB
± 0.12
± 0.12
± 0.15
50.07
± 0.15
dB
± 0.3% ± 25
± 1.0%
ppm/°C
3
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