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Part: MF5
Category:
Analog & Mixed-Signal Processing
-> Filters
-> Universal Filters
Description: Universal Monolithic Switched Capacitor Filter (discontinued)
Company: National Semiconductor Corporation
Datasheet: Download MF5 datasheet File size : 700 kB
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Datasheet text preview:
MF5 Universal Monolithic Switched Capacitor Filter
February 1995
MF5 Universal Monolithic Switched Capacitor Filter
General Description
The MF5 consists of an extremely easy to use general purpose CMOS active filter building block and an uncommitted op amp The filter building block together with an external clock and a few resistors can produce various second order functions The filter building block has 3 output pins One of the output pins can be configured to perform highpass allpass or notch functions and the remaining 2 output pins perform bandpass and lowpass functions The center frequency of the filter can be directly dependent on the clock frequency or it can depend on both clock frequency and external resistor ratios The uncommitted op amp can be used for cascading purposes for obtaining additional allH pass and notch functions or for various other applications igher order filter functions can be obtained by cascading several MF5s or by using the MF5 in conjuction with the MF10 (dual switched capacitor filter building block) The MF5 is functionally compatible with the MF10 Any of the classical filter configurations (such as Butterworth Bessel Cauer and Chebyshev) can be formed
Y Y
eatures
Low cost 14-pin DIP or 14-pin Surface Mount (SO) wide-body package Easy to use Clock to center frequency ratio accuracy g 0 6% Filter cutoff frequency stability directly dependent on external clock quality Low sensitivity to external component variations Separate highpass (or notch or allpass) bandpass lowpass outputs fo c Q range up to 200 kHz Operation up to 30 kHz (typical) Additional uncommitted op-amp
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F
Block and Connection Diagrams
TL H 5066 1
All Packages
Order Number MF5CN See NS Package Number N14A Order Number MF5CWM See NS Package Number M14B
Top View
TL H 5066 2
C1995 National Semiconductor Corporation
TL H 5066
RRD-B30M115 Printed in U S A
Absolute Maximum Ratings
p If Military Aerospace specified devices are required lease contact the National Semiconductor Sales S Office Distributors for availability and specifications upply Voltage (V a b Vb) Power Dissipation TA e 25 C (note 1) Storage Temp Soldering Information N Package 10 sec SO Package Vapor phase (60 sec ) Infrared (15 sec ) 14V 500 mW 150 C 260 C 215 C 220 C See AN-450 ``Surface Mounting Methods and Their Effect on Product Reliability'' for other methods of soldering surI face mount devices nput Voltage (any pin) Operating Temp Range MF5CN MF5CWM Vb s Vin s V a TMIN s TA s TMAX 0 C s TA s 70 C
Electrical Characteristics V a e 5V g 0 5% Vb e b5V g 0 5% unless otherwise noted Boldface limits apply over temperature TMIN s TA s TMAX For all other limits TA e 25 C T
Parameter Supply Voltage (V a b Vb) Maximum Supply Current Clock Feedthrough Filter Output Op-amp Output Min Max Clock applied to Pin 8 No Input Signal 45 10 10 60 Conditions ypical (Note 6) Tested Limit (Note 7) Design Limit (Note 8) 8 14 Units V V mA mV mV
Filter Electrical Characteristics V a e 5V g 0 5% Vb e b5V g 0 5% unless otherwise noted Boldface limits apply over temperature TMIN s TA s TMAX For all other limits TA e 25 C T
Parameter Center Frequency Range (fo) Clock Frequency Range (fCLK) Clock to Center Frequency Ratio (fCLK fo) fCLK fo Temp Coefficient Max Min Max Min Ideal Q e 10 Mode 1 Vpin9 e a 5V FCLK e 250 kHz Vpin9 e b5V FCLK e 500 kHz Conditions ypical (Note 6) 30 01 15 50 50 11 g 0 2% 100 04 g 0 2%
g 10 g 20 g 10 g 10
Tested Limit (Note 7)
Design Limit (Note 8) 20 02 10 10
Units kHz Hz MHz Hz
50 11 g 1 5% 100 04 g 1 5% ppm C ppm C % % ppm C ppm C
g0 2
Vpin9 e a 5V (50 1 CLK ratio) Vpin9 e b5V (100 1 CLK ratio)
Q Accuracy (Max) (Note 2)
Ideal Q e 10 Mode 1
Vpin9 e a 5V FCLK e 250 kHz Vpin9 e b5V FCLK e 500 kHz
b 200 b 70
Q Temperature Coefficient
Vpin9 e a 5V (50 1 CLK ratio) Vpin9 e b5V (100 1 CLK ratio)
DC Lowpass Gain Accuracy (Max) DC Offset Voltage (Max) Vos1 Vos2 Vos3 (Note 3) Vos2 Vos3
Mode 1 R1 e R2 e 10 kX
g5 0
dB mV mV mV mV mV
Vpin9 e a 5V (50 1 CLK ratio) Vpin9 e b5V (100 1 CLK ratio) 2
b 185 a 115 b 310 a 240
Filter Electrical Characteristics V a e 5V g 0 5% Vb e b5V g 0 5% unless otherwise noted Boldface limits apply over temperature TMIN s TA s TMAX For all other limits TA e 25 C (Continued)
Parameter Output Swing (Min) Dynamic Range (Note 4) Maximum Output Short Circuit Current (Note 5) Source Sink BP LP pins N AP HP pin Conditions RL e 5 kX RL e 3 5 kX Vpin9 e a 5V (50 1 CLK ratio) Vpin9 e b5V (100 1 CLK ratio) Typical (Note 6)
g4 0 g4 2
Tested Limit (Note 7)
g3 8 g3 8
Design Limit (Note 8)
Units V V dB dB mA mA
83 80 20 30
OP-AMP Electrical Characteristics V a e a 5V g 0 5% Vb e b5V g 0 5% unless other noted Boldface limits apply over temperature TMIN s TA s TMAX For all other limits TA e 25 C T
Parameter Gain Bandwidth Product Output Voltage Swing (Min) Slew Rate DC Open-Loop Gain Input Offset Voltage (Max) Input Bias Current Maximum Output Short Circuit Current (Note 5) A ogic L Source Sink RL e 3 5 kX Conditions ypical (Note 6) 25
g4 2 g3 8
Tested Limit (Note 7)
Design Limit (Note 8)
Units MHz V V ms db
70 80
g5 0 g 20
mV pA mA mA
10 20 30 TMIN s TA s TMAX Tested Limit (Note 7) 30 V a e a 5V Vb e b5V VL Sh e 0V
b3 0
Input Characteristics Boldface limits apply over temperature
T Conditions ypical (Note 6) Parameter
ll other limits TA e 25 C
Design Limit (Note 8)
Units V V V V V V
CMOS Clock Input
Min Logical ``1'' Mput Voltage In ax Logical ``0'' Input Voltage Min Logical ``1'' M Input Voltage ax Logical ``0'' Input Voltage
80 V a e a 10V Vb e 0V VL Sh e a 5V 20 20 V a e a 5V Vb e b5V VL Sh e 0V 08
TTL Clock Input
Min Logical ``1'' Mput Voltage In ax Logical ``0'' Input Voltage
Note 1 The typical junction-to-ambient thermal resistance (iJA) of the 14 pin N package is 160 C W and 82 C W for the M package ote 2 The accuracy of the Q value is a function of the center frequency (fo) This is illustrated in the curves under the heading ``Typical Performance N Characteristics'' ote 3 Vos1 Vos2 and Vos3 refer to the internal offsets as discussed in the Application Information section 3 4 Note 4 For g 5V supplies the dynamic range is referenced to 2 82V rms (4V peak) where the wideband noise over a 20 kHz bandwidth is typically 200 mV rms for N e MF5 with a 50 1 CLK ratio and 280 mV rms for the MF5 with a 100 1 CLK ratio th ote 5 The short circuit source current is measured by forcing the output that is being tested to its maximum positive voltage swing and then shorting that output to the negative supply The short circuit sink current is measured by forcing the output that is being tested to its maximum negative voltage swing and then shorting N that output to the positive supply These are the worst case conditions Note 6 Typicals are at 25 C and represent most likely parametric norm Note 7 Guaranteed and 100% tested ote 8 Guaranteed but not 100% tested These limits are not used to calculate outgoing quality levels 3
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