|Description||Advanced Imaging/communications Signal Processors|
|Company||National Semiconductor Corporation|
|Datasheet||Download N32FX164AVLJ-25 datasheet
The NS32FX164 the NS32FV16 and the NS32FX161 are high-performance 32-bit members of the Series 32000 EPTM family of National's Embedded System ProcessorsTM specifically optimized for CCITT Group 2 and Group 3 Facsimile Applications Data Modems Voice Mail Systems Laser Printers or any combination of the above Unless specified otherwise any reference to the NS32FX164 in this document applies to the NS32FV16 and the NS32FX161 as well The NS32FX164 can perform all the computations and control functions required for a stand-alone Fax system a PC add-in Fax Voice Data Modem card or a Laser Fax system It also meets the performance requirements to implement 14400 9600 and 7200 bps modems complying with CCITT V 29 and V 27 standards The NS32FV16 supports V 29 and V 27 standards as well as voice The NS32FX161 supports V 29 and V 27 standards The NS32FX164 provides a 16 Mbyte Linear external address space and a 16-bit external data bus The CPU core which is the same as that of the NS32CG16 incorporates a 32-bit ALU and instruction pipeline and an 8-byte prefetch queue Also integrated on-chip with the CPU are a DSP Module (DSPM) and a 4K-byte RAM Array (2K in the NS32FV16 and NS32FX161) The DSPM is a complete processing unit capable of autonomous operation parallel to the CPU core operation The DSPM executes programs stored in an internal on-chip Random Access Memory (RAM) and manipulates data stored either in the internal RAM in an external off-chip memory To maximize utilization of hardware resources the DSPM contains a pipelined DSP-oriented datapath and a control logic that implements a set of DSP vector commands
The NS32FX164 capabilities can be expanded by using an external floating point unit (FPU) which directly interfaces to the NS32FX164 using the slave protocol The CPU-FPU cluster features high speed execution of the floating-point instructions The NS32FX164 highly-efficient architecture combined with the NS32CG16 graphics instructions and the high-performance vector operation capability makes the device the ideal choice for PostscriptTM and Fax applicationsFeatures
Software compatible with the Series 32000 EP processors Designed around the CPU core of the NS32CG16 Pin compatible with the NS32FX16 32-bit architecture and implementation On-chip DSP Module for high-speed DSP operations Special support for graphics applications 18 graphics instructions Binary compression expansion capability for font storage using RLL encoding Pattern magnification Interface to an external BITBLT processing units for fast color BITBLT operations 4K-byte on-chip RAM array in NS32FV16 and NS32FX161) On-chip clock generator Floating-point support via the or NS32181 Optimal interface to large memory arrays via the NS32CG821 and the DP84xx family of DRAM controllers Power save mode High-speed CMOS technology 68-pin PLCC package
Series is a registered trademark of National Semiconductor Corporation EPTM and Embedded System ProcessorsTM are trademarks of National Semiconductor Corporation PostscriptTM is a trademark of Adobe Systems Inc C1995 National Semiconductor Corporation EE11267 RRD-B30M115 Printed S A2 7 Exception Acknowledge Sequences Detailed Flow Maskable Non-Maskable Interrupt Sequence 39
Output Signals Internal Propagation Delays Input Signal Requirements 4 3 Timing Diagrams APPENDIX A INSTRUCTION FORMATS APPENDIX B INSTRUCTION EXECUTION TIMES B 1 Basic and Floating-Point Instructions B 1 Equations 1 2 Notes on Table Use
1 3 Calculation of the Execution Time TEX for Basic Instructions 1 4 Calculation of the Execution Time TEX for Floating-Point Instructions B 2 Special Graphics Instructions 2 1 Execution Time Calculation for Special Graphics Instructions B 3 DSPM Instructions 99 100
FIGURE 1-1 FIGURE 2-1 FIGURE 2-2 FIGURE 2-3 FIGURE 2-4 FIGURE 2-5 FIGURE 2-6 FIGURE 2-7 FIGURE 2-8 FIGURE 2-9 CPU Block Diagram NS32FX164 Internal Registers Processor Status Register (PSR) Configuration Register (CFG) DSP Module Registers Address Map Accumulator Format Y Z Registers Format EABR Register Format OVF Register Format PARAM Register Format
FIGURE 2-10 REPEAT Register Format FIGURE 2-11 EXT Register Format FIGURE 2-12 CLSTAT Register Format FIGURE 2-13 DSPINT and DSPMASK Register Format FIGURE 2-14 NMISTAT Register Format FIGURE 2-15 NS32FX164 Address Mapping FIGURE 2-16 NS32FX164 Run-Time Environment FIGURE 2-17 General Instruction Format FIGURE 2-18 Index Byte Format FIGURE 2-19 Displacement Encodings FIGURE 2-20 Correspondence between Linear and Cartesian Addressing FIGURE by 32-Scan Line Frame Buffer FIGURE 2-22 Overlapping BITBLT Blocks FIGURE 2-23 BB Instructions Format FIGURE 2-24 BITWT Instruction Format FIGURE 2-25 EXTBLT Instruction Format FIGURE 2-26 MOVMPi Instruction Format
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