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Details, datasheet, quote on part number:NS16C552
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| Part: | NS16C552 |
| Category: | FPGAs/PLDs => FPGA (Field Programmable Gate Array) => FPGA/PLD Soft Core |
| Description: | Dual Universal Asynchronous Receiver/transmitter With Fifo's |
| Company: | National Semiconductor Corporation |
| Datasheet: | Download NS16C552 datasheet File size : 299 kB |
| Request For quote: | Find where to buy NS16C552
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Datasheet text preview:
PC16552D Dual Universal Asynchronous Receiver Transmitter with FIFOs
June 1995
PC16552D Dual Universal Asynchronous G eceiver Transmitter with FIFOs R
eneral Description
The PC16552D is a dual version of the PC16550D Universal Asynchronous Receiver Transmitter (UART) The two serial channels are completely independent except for a common CPU interface and crystal input On power-up both channels are functionally identical to the 16450 Each channel can operate with on-chip transmitter and receiver FIFOs (FIFO I mode) to relieve the CPU of excessive software overhead n FIFO mode each channel is capable of buffering 16 bytes (plus 3 bits of error data per byte in the RCVR FIFO) of data in both the transmitter and receiver All the FIFO control logic is on-chip to minimize system overhead and maximize S system efficiency ignalling for DMA transfers is done through two pins per channel (TXRDY and RXRDY) The RXRDY function is multiplexed on one pin with the OUT 2 and BAUDOUT functions The CPU can select these functions through a new E register (Alternate Function Register) ach channel performs serial-to-parallel conversion on data a characters received from a peripheral device or a MODEM nd parallel-to-serial conversion on data characters received from the CPU The CPU can read the complete status of each channel at any time Status information reported includes the type and condition of the transfer operations being performed by the DUART as well as any error T conditions (parity overrun framing or break interrupt) he DUART includes one programmable baud rate generator for each channel Each is capable of dividing the clock input by divisors of 1 to (216 b 1) and producing a 16 c clock for driving the internal transmitter logic Provisions are also included to use this 16 c clock to drive the receiver a logic The DUART has complete MODEM-control capability nd a processor-interrupt system Interrupts can be programmed to the user's requirements minimizing the comT puting required to handle the communications link he DUART is fabricated using National Semiconductor's advanced M2CMOSTM
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eatures
Dual independent UARTs Capable of running all existing 16450 and PC16550D software After reset all registers are identical to the 16450 register set Read and write cycle times of 84 ns In the FIFO mode transmitter and receiver are each buffered with 16-byte FIFOs to reduce the number of interrupts presented to the CPU Holding and shift registers in the 16450 Mode eliminate the need for precise synchronization between the CPU and serial data Adds or deletes standard asynchronous communication bits (start stop and parity) to or from the serial data a Independently controlled transmit receive line status nd data set interrupts Programmable baud generators divide any input clock by 1 to (216 b 1) and generate the 16 c clock a MODEM control functions (CTS RTS DSR DTR RI nd DCD) Ful5 programmable serial-interface characteristics ly - 6- 7- or 8-bit characters Even odd or no-parity bit generation and detection 1- 1 - or 2-stop bit generation Baud generation (DC to 1 5M baud) with 16 c clock False start bit detection Complete status reporting capabilities TRI-STATE TTL drive for the data and control buses Line break generation and detection Internal diagnostic capabilities L oopback controls for communications link fault isolation Break parity overrun framing error simulation Full prioritized interrupt system controls
ote This part is patented
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F also be reset to 16450 Mode under software control Can N
RI-STATE is a registered trademark of National Semiconductor Corporation M2CMOSTM is a trademark of National Semiconductor Corporation
C1995 National Semiconductor Corporation
TL C 9426
RRD-B30M75 Printed in U S A
Table of Contents
1 0 ABSOLUTE MAXIMUM RATINGS 2 0 DC ELECTRICAL CHARACTERISTICS 3 0 AC ELECTRICAL CHARACTERISTICS 4 0 TIMING WAVEFORMS 5 0 BLOCK DIAGRAM OF A SINGLE SERIAL CHANNEL 6 0 PIN DESCRIPTIONS 6 1 Input Signals 6 2 Output Signals 6 3 Input Output Signals 6 4 Clock Signals 6 5 Power 7 0 CONNECTION DIAGRAM 8 0 REGISTERS 8 1 Line Control Register 8 2 Typical Clock Circuits 8 0 REGISTERS (Continued) 8 3 Programmable Baud Generator 8 4 Line Status Register 8 5 FIFO Control Register 8 6 Interrupt Identification Register 8 7 Interrupt Enable Register 8 8 Modem Control Register 8 9 Modem Status Register 8 10 Alternate Function Register 8 11 Scratchpad Register 9 0 FIFO Mode Operation 9 1 FIFO Interrupt Operation 9 2 FIFO Polled Operation 10 0 ORDERING INFORMATION
Basic Configuration
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1 0 Absolute Maximum Ratings
Temperature under Bias Storage Temperature All Input or Output Voltages 2 with Respect to VSS Power Dissipation
b 65
0 C to a 70 C C to a 150 C
b 0 5V to a 7 0V
Note Maximum ratings indicate limits beyond which permanent damage may occur Continuous operation at these limits is not intended and should be limited to those conditions specified under DC electrical characteristics
1W
0 DC Electrical Characteristics
TA e 0 C to a 70 C VDD e a 5V g 10% VSS e 0V unless otherwise specified Symbol VILX VIHX VIL VIH VOL VOH ICC(AV) Parameter Clock Input Low Voltage Clock Input High Voltage Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Average Power Supply Current IOL e 1 6 mA on all (Note 1) IOH e b1 mA (Note 1) VDD e 5 5V No Loads on Output C S S RD WR IN DSR DCD CTS RI e 2V All Other Inputs e 0 8V XIN e 24 MHz Divisor e EFFF VDD e 5 5V VSS e 0V VIN e 0V 5 5V VDD e 5 5V VSS e 0V VOUT e 0V 5 5V 1) Chip Deselected 2) WRITE Mode C hip Selected 24 Conditions Min
b0 5
Max 08 VCC 08 VCC 04
Units V V V V V V
2
b0 5
2
3
0
mA
IIL ICL IOZ
Input Leakage Clock Leakage TRI-STATE Leakage
g 10 g 10
mA mA
g 20
mA
VILMR VIHMR
Note 2 TA e 25 C
MR Schmitt VIL MR Schmitt VIH 2
08
V V
Note 1 Does not apply to XOUT
Capacitance TA e 25 C
Symbol CXIN CXOUT CIN COUT CI O
VDD e VSS e 0V Conditions Min Typ 7 fc e 1 MHz Unmeasured Pins Returned to VSS 7 5 6 10 Max 9 9 7 8 12 Units pF pF pF pF pF
Parameter Clock Input Capacitance Clock Output Capacitance Input Capacitance Output Capacitance Input Output Capacitance
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