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Details, datasheet, quote on part number:NS32202-10
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Datasheet text preview:
NS32202-10 Interrupt Control Unit
July 1991
NS32202-10 Interrupt Control Unit
General Description
The NS32202 Interrupt Control Unit (ICU) is the interrupt controller for the Series 32000 microprocessor family It is a support circuit that minimizes the software and real-time overhead required to handle multi-level prioritized interrupts A single NS32202 manages up to 16 interrupt sources esolves interrupt priorities andsuppliesasingle-byteinterrupt T vector to the CPU 1 he NS32202 can operate in either of two data bus modes 6-bit or 8-bit In the 16-bit mode eight hardware and eight 1 software interrupt positions are available In the 8-bit mode 6 hardware interrupt positions are available 8 of which can be used as software interrupts In this mode up to 16 additional ICUs may be cascaded to handle a maximum of 256 T interrupts wo 16-bit counters which may be concatenated under program control into a single 32-bit counter are also available for real-time applications
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eatures
16 maskable interrupt sources cascadable to 256 Programmable 8- or 16-bit data bus mode Edge or level triggering for each hardware interrupt with individually selectable polarities 8 software interrupts Fixed or rotating priority modes Two 16-bit DC to 10 MHz counters that may be concatenated into a single 32-bit counter Optional 8-bit I O port available in 8-bit data bus mode High-speed XMOSTM technology Single a5V supply 40-pin dual in-line package
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Basic System Configuration
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Series 32000 is a registered trademark of National Semiconductor Corp X C MOSTM is a trademark of National Semiconductor Corp
1995 National Semiconductor Corporation
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RRD-B30M105 Printed in U S A
Table of Contents
1 0 PRODUCT INTRODUCTION 1 1 I O Buffers 1 2 Read Write Logic and Decoders 1 3 Timing and Control 1 4 Priority Control 1 5 Counters 2 0 FUNCTIONAL DESCRIPTION 2 1 Reset 2 2 Initialization 2 3 Vectored Interrupt Handling 2 3 1 Non-Cascaded Operation 2 3 2 Cascade Operation 2 4 Internal ICU Operating Sequence 2 5 Interrupt Priority Modes 2 5 1 Fixed Priority Mode 2 5 2 Auto-Rotate Mode 2 5 3 Special Mask Mode 2 5 4 Polling Mode 3 0 ARCHITECTURAL DESCRIPTION 3 1 HVCT - Hardware Vector Register (R0) 3 2 SVCT - Software Vector Register (R1) 3 3 ELTG - Edge Level Triggering Registers (R2 R3) 3 4 TPL - Triggering Polarity Registers (R4 R5) 3 5 IPND - Interrupt Pending Registers (R6 R7) 3 6 ISRV - Interrupt In-Service Registers (R8 R9) 3 7 IMSK - Interrupt Mask Registers (R10 R11) 3 8 CSRC - Cascaded Source Registers (R12 R13) 3 0 ARCHITECTURAL DESCRIPTION (Continued) 3 9 FPRT - First Priority Registers (R14 R15) 3 10 MCTL - Mode Control Register (R16) 3 11 OSCASN - Output Clock Assignment (R17) 3 12 CIPTR - Counter Interrupt Pointer Register (R18) 3 13 PDAT - Port Dada Register (R19) 3 14 IPS - Interrupt Port Select Register (R20) 3 15 PDIR - Port Direction Register (R21) 3 16 CCTL - Counter Control Register (R22) 3 17 CICTL - Counter Interrupt Control Register (R23) 3 18 LCSV HCSV - L-Counter Starting Value H-Counter Starting Value Registers (R24 R25 R26 and R27) 3 19 LCCV HCCV - L-Counter Current Value H-Counter Current Value Registers (R28 R29 R30 and R31) 3 20 Register Initialization 4 0 DEVICE SPECIFICATIONS 4 1 NS32202 Pin Descriptions 4 1 1 Power Supply 4 1 2 Input Signals 4 1 3 Output Signals 4 1 4 Input Output Signals 4 2 Absolute Maximum Ratings 4 3 Electrical Characteristics 4 4 Switching Characteristics 4 4 1 Definitions 4 4 1 1 Timing Tables 4 4 1 2 Timing Diagrams
List of Illustrations
NS32202 ICU Block Diagram Counter Output Signals in Pulsed Form and Square Waveform for Three Different Initial Values Counter Configuration and Basic Operations Interrupt Control Unit Connections in 16-Bit Bus Mode Interrupt Control Unit Connections in 8-Bit Bus Mode Cascaded Interrupt Control Unit Connections in 8-Bit Bus Mode CPU Interrupt Acknowledge Sequence Interrupt Dispatch and Cascade Tables CPU Return from Interrupt Sequence ICU Interrupt Acknowledge Sequence ICU Return from Interrupt Sequence ICU Internal Registers HVCT Register Data Coding Recommended ICU's Initialization Sequence NS32202 ICU Connection Diagram Timing Specification Standard READ INTA Cycle Write Cycle Interrupt Timing in Edge Triggering Mode Interrupt Timing in Level Triggering Mode External Interrupt-Sampling-Clock to be Provided at Pin COUT SCIN When in Test Mode Internal Interrupt-Sampling-Clock to be Provided at Pin COUT SCIN Relationship Between Clock Input at Pin CLK and Counter Output Signals at Pins COUT SCIN or G0 R0 G3 R6 in Both Pulsed Form and Square Waveform 1-1 1-2 1-3 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 3-1 3-2 3-3 4-1 4-2 4-3 4-4 4-5 4-6 4-7 4-8 4-9
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1 0 Product Introduction
The NS32202 ICU functions as an overall manager in an interrupt-oriented system environment Its many features and options permit the design of sophisticated interrupt sysFems t Aigure 1 1 shows the internal organization of the NS32202 s shown the NS32202 is divided into five functional 1 blocks These are described in the following paragraphs 1 I O BUFFERS AND LATCHES The I O Buffers and Latches block is the interface with the system data bus It contains bidirectional buffers for the data I O pins It also contains registers and logic circuits that control the operation of pins G0 IR0 G7 IR14 1 when the ICU is in the 8-bit bus mode 2 READ WRITE LOGIC AND DECODERS The Read Write Logic and Decoders manage all internal C and external data transfers for the ICU These include Data ontrol and Status Transfers This circuit accepts inputs from the CPU address and control buses In turn it issues 1 commands to access the internal registers of the ICU 3 TIMING AND CONTROL The Timing and Control Block contains status elements that select the ICU operating mode It also contains state machines that generate all the necessary sequencing and control signals 4 PRIORITY CONTROL The Priority Control Block contains 16 units one for each interrupt position These units provide the following functions Sensing the various forms of hardware interrupt signals e g level (high low) or edge (rising falling) Resolving priorities and generating an interrupt request to the CPU Handling cascaded arrangements Enabling software interrupts Providing for an automatic return from interrupt Enabling the assignment of any interrupt position to the internal counters Providing for rearrangement of priorities by assigning the first priority to any interrupt position Enabling automatic rotation of priorities 1 5 COUNTERS This block contains two 16-bit counters called the H-counter and the L-counter These are down counters that count from an initial value to zero Both counters have a 16-bit register (designated HCSV and LCSV) for loading their restarting values They also have registers containing the current count values (HCCV and LCCV) Both sets of registers are fully described in Section 3 T 1
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FIGURE 1 1 NS32202 ICU Block Diagram
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