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Details, datasheet, quote on part number:NS32490D
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| Part: | NS32490D |
| Category: | Communication => Network => Ethernet/DS1/E1 (T1/E1) => Controllers |
| Description: | Nic Network Interface Controller |
| Company: | National Semiconductor Corporation |
| Datasheet: | Download NS32490D datasheet File size : 706 kB |
| Request For quote: | Find where to buy NS32490D
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Datasheet text preview:
DP8390D NS32490D NIC Network Interface Controller
July 1995
DP8390D NS32490D NIC Network Interface Controller
General Description
The DP8390D NS32490D Network Interface Controller (NIC) is a microCMOS VLSI device designed to ease interfacing with CSMA CD type local area networks including Ethernet Thin Ethernet (Cheapernet) and StarLAN The NIC implements all Media Access Control (MAC) layer functions for transmission and reception of packets in accordance with the IEEE 802 3 Standard Unique dual DMA channels and an internal FIFO provide a simple yet efficient packet management design To minimize system parts count and cost all bus arbitration and memory support logic T are integrated into the NIC he NIC is the heart of a three chip set that implements the complete IEEE 802 3 protocol and node electronics as shown below The others include the DP8391 Serial Network Interface (SNI) and the DP8392 Coaxial Transceiver F Interface (CTI)
Table of Contents
1 0 SYSTEM DIAGRAM 2 0 BLOCK DIAGRAM 3 0 FUNCTIONAL DESCRIPTION 4 0 DRANSMIT RECEIVE PACKET ENCAPSULATION T ECAPSULATION 5 0 PIN DESCRIPTIONS 6 0 DIRECT MEMORY ACCESS CONTROL (DMA) 7 0 PACKET RECEPTION 8 0 PACKET TRANSMISSION 9 0 REMOTE DMA 10 0 INTERNAL REGISTERS 11 0 INITIALIZATION PROCEDURES 12 0 LOOPBACK DIAGNOSTICS 13 0 BUS ARBITRATION AND TIMING 14 0 PRELIMINARY ELECTRICAL CHARACTERISTICS 15 0 SWITCHING CHARACTERISTICS 16 0 PHYSICAL DIMENSIONS
eatures
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S Compatible with IEEE 802 3 Ethernet II Thin Ethernet tarLAN Interfaces with 8- 16- and 32-bit microprocessor systems Implements simple versatile buffer management Requires single 5V supply Utilizes low power microCMOS process Includes Two 16-bit DMA channels 16-byte internal FIFO with programmable threshold Network statistics storage Supports physical multicast and broadcast address filtering Provides 3 levels of loopback Utilizes independent system and network clocks
1 0 System Diagram
IEEE 802 3 Compatible Ethernet Thin Ethernet Local Area Network Chip Set
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C TRI-STATE is a registered trademark of National Semiconductor Corporation
1995 National Semiconductor Corporation
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RRD-B30M105 Printed in U S A
2 0 Block Diagram
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FIGURE 1
3 0 Functional Description
(Refer to Figure 1 ) RECEIVE DESERIALIZER The Receive Deserializer is activated when the input signal Carrier Sense is asserted to allow incoming bits to be shifted into the shift register by the receive clock The serial receive data is also routed to the CRC generator checker The Receive Deserializer includes a synch detector which detects the SFD (Start of Frame Delimiter) to establish where byte boundaries within the serial bit stream are located After every eight receive clocks the byte wide data is transferred to the 16-byte FIFO and the Receive Byte Count is incremented The first six bytes after the SFD are checked for valid comparison by the Address Recognition Logic If the Address Recognition Logic does not recognize C the packet the FIFO is cleared RC GENERATOR CHECKER During transmission the CRC logic generates a local CRC field for the transmitted bit sequence The CRC encodes all fields after the synch byte The CRC is shifted out MSB first following the last transmit byte During reception the CRC logic generates a CRC field from the incoming packet This local CRC is serially compared to the incoming CRC appended to the end of the packet by the transmitting node If the local and received CRC match a specific pattern will be generated and decoded to indicate no data errors Transr mission errors result in a different pattern and are detected T sulting in rejection of a packet e RANSMIT SERIALIZER The Transmit Serializer reads parallel data from the FIFO and serializes it for transmission The serializer is clocked by 2 the transmit clock generated by the Serial Network Interface (DP8391) The serial data is also shifted into the CRC generator checker At the beginning of each transmission the Preamble and Synch Generator append 62 bits of 1 0 preamble and a 1 1 synch pattern After the last data byte of the packet has been serialized the 32-bit FCS field is shifted directly out of the CRC generator In the event of a collision the Preamble and Synch generator is used to generate a 32-bit JAM pattern of all 1's ADDRESS RECOGNITION LOGIC The address recognition logic compares the Destination Address Field (first 6 bytes of the received packet) to the PhysI ical address registers stored in the Address Register Array f any one of the six bytes does not match the pre-programmed physical address the Protocol Control Logic rejects the packet All multicast destination addresses are filtered using a hashing technique (See register description ) If the multicast address indexes a bit that has been set in the filter bit array of the Multicast Address Register Array the packet is accepted otherwise it is rejected by the Protocol Control Logic Each destination address is also checked F for all 1's which is the reserved broadcast address IFO AND FIFO CONTROL LOGIC The NIC features a 16-byte FIFO During transmission the DMA writes data into the FIFO and the Transmit Serializer reads data from the FIFO and transmits it During reception the Receive Deserializer writes data into the FIFO and the DMA reads data from the FIFO The FIFO control logic is used to count the number of bytes in the FIFO so that after r a preset level the DMA can begin a bus access and write ead data to from the FIFO before a FIFO underflow overflow occurs
3 0 Functional Description (Continued)
Because the NIC must buffer the Address field of each incoming packet to determine whether the packet matches its Physical Address Registers or maps to one of its Multicast Registers the first local DMA transfer does not occur until 8 T bytes have accumulated in the FIFO t o assure that there is no overwriting of data in the FIFO he FIFO logic flags a FIFO overrun as the 13th byte is written into the FIFO this effectively shortens the FIFO to 13 bytes In addition the FIFO logic operates differently in Byte Mode than in Word Mode In Byte Mode a threshold is indicated when the n a 1 byte has entered the FIFO thus with an 8-byte threshold the NIC issues Bus Request (BREQ) when the 9th byte has entered the FIFO For Word Mode BREQ is not generated until the n a 2 bytes have entered the FIFO Thus with a 4 word threshold (equivalent to an 8-byte threshold) BREQ is issued when the 10th byte P has entered the FIFO ROTOCOL PLA The protocol PLA is responsible for implementing the IEEE 802 3 protocol including collision recovery with random backoff The Protocol PLA also formats packets during transmission and strips preamble and synch during recepD tion MA AND BUFFER CONTROL LOGIC The DMA and Buffer Control Logic is used to control two 16-bit DMA channels During reception the Local DMA stores packets in a receive buffer ring located in buffer memory During transmission the Local DMA uses programmed pointer and length registers to transfer a packet from local buffer memory to the FIFO A second DMA channel is used as a slave DMA to transfer data between the local buffer memory and the host system The Local DMA and Remote DMA are internally arbitrated with the Local DMA channel having highest priority Both DMA channels use a common external bus clock to generate all required bus timing External arbitration is performed with a standard bus request bus acknowledge handshake protocol 4 two bit pattern This allows any preceding preamble within D the SFD to be used for phase locking ESTINATION ADDRESS The destination address indicates the destination of the packet on the network and is used to filter unwanted packets from reaching a node There are three types of address formats supported by the NIC physical multicast and broadcast The physical address is a unique address that corresponds only to a single node All physical addresses have an MSB of ``0'' These addresses are compared to the internally stored physical address registers Each bit in the destination address must match in order for the NIC to accept the packet Multicast addresses begin with an MSB of ``1'' The DP8390D filters multicast addresses using a standard hashing algorithm that maps all multicast addresses into a 6-bit value This 6-bit value indexes a 64-bit array that filters the value If the address consists of all 1's it is a broadcast address indicating that the packet is intended for all nodes A promiscuous mode allows reception of all packets the destination address is not required to match any filters Physical broadcast multicast and promiscuous adS dress modes can be selected OURCE ADDRESS The source address is the physical address of the node that sent the packet Source addresses cannot be multicast or broadcast addresses This field is simply passed to buffer L memory ENGTH FIELD The 2-byte length field indicates the number of bytes that are contained in the data field of the packet This field is not D interpreted by the NIC ATA FIELD M The data field consists of anywhere from 46 to 1500 bytes essages longer than 1500 bytes need to be broken into multiple packets Messages shorter than 46 bytes will require appending a pad to bring the data field to the minimum length of 46 bytes If the data field is padded the number of valid data bytes is indicated in the length field The NIC o does not strip or append pad bytes for short packets F r check for oversize packets CS FIELD The Frame Check Sequence (FCS) is a 32-bit CRC field calculated and appended to a packet during transmission to allow detection of errors when a packet is received During reception error free packets result in a specific pattern in the CRC generator Packets with improper CRC will be rejected The AUTODIN II (X32 a X26 a X23 a X22 a X16 a X12 a X11 a X10 a X8 a X7 a X5 a X4 a X2 a X1 a 1) polynomial is used for the CRC calculations T
0 Transmit Receive Packet Encapsulation Decapsulation
A standard IEEE 802 3 packet consists of the following fields preamble Start of Frame Delimiter (SFD) destination address source address length data and Frame Check Sequence (FCS) The typical format is shown in Figure 2 T he packets are Manchester encoded and decoded by the DP8391 SNI and transferred serially to the NIC using NRZ data with a clock All fields are of fixed length except for the S data field The NIC generates and appends the preamble FD and FCS field during transmission The Preamble and SFD fields are stripped during reception (The CRC is passed through to buffer memory during reception ) PREAMBLE AND START OF FRAME DELIMITER (SFD) The Manchester encoded alternating 1 0 preamble field is used by the SNI (DP8391) to acquire bit synchronization with an incoming packet When transmitted each packet contains 62 bits of alternating 1 0 preamble Some of this preamble will be lost as the packet travels through the network The preamble field is stripped by the NIC Byte alignment is performed with the Start of Frame Delimiter (SFD) pattern which consists of two consecutive 1's The NIC does not treat the SFD pattern as a byte it detects only the
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