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Details, datasheet, quote on part number:RS-170
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| Part: | RS-170 |
| Category: | Analog & Mixed-Signal Processing => Amplifiers => High Speed/Video Amplifiers |
| Description: | Programmable Video SYNC Generator |
| Company: | National Semiconductor Corporation |
| Datasheet: | Download RS-170 datasheet File size : 348 kB |
| Request For quote: | Find where to buy RS-170
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Datasheet text preview:
LM1882 · 54ACT715 · LM1882-R · 54ACT715-R Programmable Video Sync Generator
December 1998
LM1882·54ACT715 LM1882-R · 54ACT715-R Programmable Video Sync Generator
General Description
The 'ACT715/LM1882 and 'ACT715-R/LM1882-R are 20-pin TTL-input compatible devices capable of generating Horizontal, Vertical and Composite Sync and Blank signals for televisions and monitors. All pulse widths are completely definable by the user. The devices are capable of generating signals for both interlaced and noninterlaced modes of operation. Equalization and serration pulses can be introduced into the Composite Sync signal when needed. Four additional signals can also be made available when Composite Sync or Blank are used. These signals can be used to generate horizontal or vertical gating pulses, cursor position or vertical Interrupt signal. These devices make no assumptions concerning the system architecture. Line rate and field/frame rate are all a function of the values programmed into the data registers, the status register, and the input clock frequency. The 'ACT715/LM1882 is mask programmed to default to a Clock Disable state. Bit 10 of the Status Register, Register 0, defaults to a logic "0". This facilitates (re)programming before operation. The 'ACT715-R/LM1882-R is the same as the 'ACT715/ LM1882 in all respects except that the 'ACT715-R/ LM1882-R is mask programmed to default to a Clock Enabled state. Bit 10 of the Status Register defaults to a logic "1". Although completely (re)programmable, the 'ACT715-R/ LM1882-R version is better suited for applications using the default 14.31818 MHz RS-170 register values. This feature allows power-up directly into operation, following a single CLEAR pulse.
Features
n Maximum Input Clock Frequency > 130 MHz n Interlaced and non-interlaced formats available n Separate or composite horizontal and vertical Sync and Blank signals available n Complete control of pulse width via register programming n All inputs are TTL compatible n 8 mA drive on all outputs n Default RS170/NTSC values mask programmed into registers n 4 KV minimum ESD immunity n 'ACT715-R/LM1882-R is mask programmed to default to a Clock Enable state for easier start-up into 14.31818 MHz RS170 timing
Connection Diagrams
Pin Assignment for DIP and SOIC Pin Assignment for LCC
DS100232-1
Order Number LM1882CN or LM1882CM For Default RS-170, Order Number LM1882-RCN or LM1882-RCM
DS100232-2
TRI-STATE ® is a registered trademark of National Semiconductor Corporation. FACTTM is a trademark of Fairchild Semiconductor Corporation.
© 1998 National Semiconductor Corporation
DS100232
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Logic Block Diagram
DS100232-3
Pin Description
There are a Total of 13 inputs and 5 outputs on the 'ACT715/ LM1882. Data Inputs D0 D7: The Data Input pins connect to the Address Register and the Data Input Register. ADDR/DATA: The ADDR/DATA signal is latched into the device on the falling edge of the LOAD signal. The signal determines if an address (0) or data (1) is present on the data bus. L/HBYTE: The L/HBYTE signal is latched into the device on the falling edge of the LOAD signal. The signal determines if data will be read into the 8 LSB's (0) or the 4 MSB's (1) of the Data Registers. A 1 on this pin when an ADDR/DATA is a 0 enables Auto-Load Mode. LOAD: The LOAD control pin loads data into the Address or Data Registers on the rising edge. ADDR/DATA and L/HBYTE data is loaded into the device on the falling edge of the LOAD. The LOAD pin has been implemented as a Schmitt trigger input for better noise immunity. CLOCK: System CLOCK input from which all timing is derived. The clock pin has been implemented as a Schmitt trigger for better noise immunity. The CLOCK and the LOAD signal are asynchronous and independent. Output state changes occur on the falling edge of CLOCK. CLR: The CLEAR pin is an asynchronous input that initializes the device when it is HIGH. Initialization consists of setting all registers to their mask programmed values, and initializing all counters, comparators and registers. The CLEAR pin has been implemented as a Schmitt trigger for better noise immunity. A CLEAR pulse should be asserted by the user immediately after power-up to ensure proper initialization of the registers -- even if the user plans to (re)program the device.
Note: A CLEAR pulse will disable the CLOCK on the 'ACT715/LM1882 and will enable the CLOCK on the 'ACT715-R/LM1882-R.
ODD/EVEN: Output that identifies if display is in odd (HIGH) or even (LOW) field of interlace when device is in interlaced mode of operation. In noninterlaced mode of operation this output is always HIGH. Data can be serially scanned out on this pin during Scan Mode. VCSYNC: Outputs Vertical or Composite Sync signal based on value of the Status Register. Equalization and Serration pulses will (if enabled) be output on the VCSYNC signal in composite mode only. VCBLANK: Outputs Vertical or Composite Blanking signal based on value of the Status Register. HBLHDR: Outputs Horizontal Blanking signal, Horizontal Gating signal or Cursor Position based on value of the Status Register. HSYNVDR: Outputs Horizontal Sync signal, Vertical Gating signal or Vertical Interrupt signal based on value of Status Register.
Register Description
All of the data registers are 12 bits wide. Width's of all pulses are defined by specifying the start count and end count of all pulses. Horizontal pulses are specified with-respect-to the number of clock pulses per line and vertical pulses are specified with-respect-to the number of lines per frame. REG0 -- STATUS REGISTER The Status Register controls the mode of operation, the signals that are output and the polarity of these outputs. The default value for the Status Register is 0 (000 Hex) for the 'ACT715/LM1882 and is "1024" (400 Hex) for the 'ACT715-R/LM1882-R.
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Register Description Bits 0 2
B2 0 0 0 0 1 1 1 1 B1 0 0 1 1 0 0 1 1 B0 0 1 0 1 0 1 0 1 VCBLANK CBLANK VBLANK CBLANK VBLANK CBLANK VBLANK CBLANK VBLANK
(Continued)
VCSYNC CSYNC CSYNC VSYNC VSYNC CSYNC CSYNC VSYNC VSYNC
HBLHDR HSYNVDR HGATE HBLANK HGATE HBLANK CURSOR HBLANK CURSOR HBLANK VGATE VGATE HSYNC HSYNC VINT VINT HSYNC HSYNC
HORIZONTAL INTERVAL REGISTERS The Horizontal Interval Registers determine the number of clock cycles per line and the characteristics of the Horizontal Sync and Blank pulses. REG1 -- Horizontal Front Porch REG2 -- REG3 -- REG4 -- Horizontal Sync Pulse End Time Horizontal Blanking Width # of Clocks per Horizontal Interval Width Line
(DEFAULT)
Bits 3 4
B4 0 0 1 1 B3 0 1 0 1 Mode of Operation Interlaced Double Serration and Equalization Non Interlaced Double Serration Illegal State Non Interlaced Single Serration and Equalization
VERTICAL INTERVAL REGISTERS The Vertical Interval Registers determine the number of lines per frame, and the characteristics of the Vertical Blank and Sync Pulses. REG5 -- Vertical Front Porch REG6 -- Vertical Sync Pulse End Time REG7 -- REG8 -- Vertical Blanking Width Vertical Interval Width
# of Lines per Frame
(DEFAULT)
EQUALIZATION AND SERRATION PULSE SPECIFICATION REGISTERS These registers determine the width of equalization and serration pulses and the vertical interval over which they occur. REG 9 -- Equalization Pulse Width End Time REG10 -- Serration Pulse Width End Time REG11 -- Equalization/Serration Pulse Vertical Interval Start Time REG12 -- Equalization/Serration Pulse Vertical Interval End Time VERTICAL INTERRUPT SPECIFICATION REGISTERS These Registers determine the width of the Vertical Interrupt signal if used. REG13 -- Vertical Interrupt Activate Time REG14 -- Vertical Interrupt Deactivate Time
Double Equalization and Serration mode will output equalization and serration pulses at twice the HSYNC frequency (i.e., 2 equalization or serration pulses for every HSYNC pulse). Single Equalization and Serration mode will output an equalization or serration pulse for every HSYNC pulse. In Interlaced mode equalization and serration pulses will be output during the VBLANK period of every odd and even field. Interlaced Single Equalization and Serration mode is not possible with this part. Bits 5 8 Bits 5 through 8 control the polarity of the outputs. A value of zero in these bit locations indicates an output pulse active LOW. A value of 1 indicates an active HIGH pulse. B5 -- B6 -- B7 -- B8 -- VCBLANK Polarity VCSYNC Polarity HBLHDR Polarity HSYNVDR Polarity
CURSOR LOCATION REGISTERS These 4 registers determine the cursor position location, or they generate separate Horizontal and Vertical Gating signals. REG15 -- REG16 -- REG17 -- REG18 -- Horizontal Cursor Position Start Time Horizontal Cursor Position End Time Vertical Cursor Position Start Time Vertical Cursor Position End Time
Bits 9 11 Bits 9 through 11 enable several different features of the device. B9 -- Enable Equalization/Serration Pulses (0) Disable Equalization/Serration Pulses (1) B10 -- Disable System Clock (0) Enable System Clock (1) Default values for B10 are "0" in the 'ACT715/ LM1882 and "1" in the 'ACT715-R/LM1882-R. B11 -- Disable Counter Test Mode (0) Enable Counter Test Mode (1) This bit is not intended for the user but is for internal testing only.
Signal Specification
HORIZONTAL SYNC AND BLANK SPECIFICATIONS All horizontal signals are defined by a start and end time. The start and end times are specified in number of clock cycles per line. The start of the horizontal line is considered pulse 1 not 0. All values of the horizontal timing registers are referenced to the falling edge of the Horizontal Blank signal (see Figure 1). Since the first CLOCK edge, CLOCK #1, causes the first falling edge of the Horizontal Blank reference pulse, edges referenced to this first Horizontal edge are n + 1 CLOCKs away, where "n" is the width of the timing in question. Registers 1, 2, and 3 are programmed in this manner. The horizontal counters start at 1 and count until HMAX. The value of HMAX must be divisible by 2. This limitation is im3 www.national.com
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