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Details, datasheet, quote on part number:TP3054J
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| Part: | TP3054J |
| Category: | Communication => Telephony => Analog Line Card |
| Description: | TP3054 - TP3052, TP3053, TP3054, TP3057, Enhanced Serial Interface Codec/filter Combo Family, Package: Soic Wide, Pin Nb=16 |
| Company: | National Semiconductor Corporation |
| Datasheet: | Download TP3054J datasheet File size : 257 kB |
| Request For quote: | Find where to buy TP3054J
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Datasheet text preview:
TP3054 TP3057 ``Enhanced'' Serial Interface CODEC Filter COMBO Family
August 1994
TP3054 TP3057 ``Enhanced'' Serial Interface CODEC Filter COMBO Family
General Description
The TP3054 TP3057 family consists of m-law and A-law monolithic PCM CODEC filters utilizing the A D and D A conversion architecture shown in Figure 1 and a serial PCM interface The devices are fabricated using National's adT vanced double-poly CMOS process (microCMOS) he encode portion of each device consists of an input gain adjust amplifier an active RC pre-filter which eliminates very high frequency noise prior to entering a switched-capacitor band-pass filter that rejects signals below 200 Hz and above 3400 Hz Also included are auto-zero circuitry and a companding coder which samples the filtered signal and encodes it in the companded m-law or A-law PCM format The decode portion of each device consists of an expanding decoder which reconstructs the analog signal from the companded m-law or A-law code a low-pass filter which corrects for the sin x x response of the decoder output and rejects signals above 3400 Hz followed by a single-ended T power amplifier capable of driving low impedance loads he devices require two 1 536 MHz 1 544 MHz or 2 048 MHz transmit and receive master clocks which may be asynchronous transmit and receive bit clocks which may vary from 64 kHz to 2 048 MHz and transmit and receive frame sync pulses The timing of the frame sync pulses and PCM data is compatible with both industry standard formats
Y
eatures
Complete CODEC and filtering system (COMBO) incT ding lu ransmit high-pass and low-pass filtering Receive low-pass filter with sin x x correction Active RC noise filters m-law or A-law compatible COder and DECoder Internal precision voltage reference Serial I O interface Internal auto-zero circuitry m-law 16-pin TP3054 A-law 16-pin TP3057 Designed for D3 D4 and CCITT applications g 5V operation Low operating power typically 50 mW Power-down standby mode typically 3 mW Automatic power-down TTL or CMOS compatible digital interfaces Maximizes line interface card circuit density Dual-In-Line or surface mount packages See also AN-370 ``Techniques for Designing with CODEC Filter COMBO Circuits''
Y Y Y Y Y Y Y Y Y Y Y
F
Connection Diagrams
Dual-In-Line Package Plastic Chip Carriers
TL H 5510 1
Top View Order Number TP3054J or TP3057J See NS Package Number J16A Order Number TP3054N or TP3057N See NS Package Number N16A Order Number TP3054WM or TP3057WM See NS Package Number M16B
TL H 5510 10
Top View Order Number TP3057V See NS Package Number V20A
C COMBO and TRI-STATE are registered trademarks of National Semiconductor Corporation 1995 National Semiconductor Corporation TL H 5510 RRD-B30M125 Printed in U S A
Block Diagram
FIGURE 1
TL H 5510 2
Pin Description
Symbol VBB G NDA V FRO V
CC
Function V Negative power supply pin BB e b 5V g 5% Analog ground All signals are referenced to this pin Analog output of the receive power amplifier V Positive power supply pin CC e a 5V g 5% Receive frame sync pulse which enables BCLKR to shift PCM data into DR FSR is an 8 kHz pulse train See Figures 2 and 3 for timing details Receive data input PCM data is shifted into DR following the FSR leading edge
Symbol
M CLKX
Function should be synchronous with MCLKX for best performance When MCLKR is connected continuously low MCLKX is selected for all internal timing When MCLKR is connected continuously high the device is powered down 1 Transmit master clock Must be 1 536 MHz 544 MHz or 2 048 MHz May be asynchronous with MCLKR Best performance is realized from synchronous operation Transmit frame sync pulse input which enables BCLKX to shift out the PCM data on DX FSX is an 8 kHz pulse train see Figures 2 and 3 for timing details The bit clock which shifts out the PCM data on DX May vary from 64 kHz to 2 048 MHz but must be synchronous with MCLKX The TRI-STATE abled by FSX
F SR
F SX
D
R
B CLKX D
X
B
CLKR CLKSEL The bit clock which shifts data into DR after the FSR leading edge May vary from 64 kHz to 2 048 MHz Alternatively may be a logic input which selects either 1 536 MHz 1 544 MHz or 2 048 MHz for master clock in synchronous mode and BCLKX is used for both transmit and reM ceive directions (see Table I) CLKR PDN Receive master clock Must be M 1 536 MHz 1 544 MHz or 2 048 MHz ay be asynchronous with MCLKX but
PCM data output which is en-
T SX G SX V VFXIb FXI a 2
Open drain output which pulses low during the encoder time slot U Analog output of the transmit input amplifier sed to externally set gain Inverting input of the transmit input amplifier Non-inverting input of the transmit input amplifier
Functional Description
POWER-UP When power is first applied power-on reset circuitry initializes the COMBO and places it into a power-down state All non-essential circuits are deactivated and the DX and VFRO outputs are put in high impedance states To power-up the device a logical low level or clock must be applied to the MCLKR PDN pin and FSX and or FSR pulses must be present Thus 2 power-down control modes are available The first is to pull the MCLKR PDN pin high the alternative is to hold both FSX and FSR inputs continuously low the device will power-down approximately 1 ms after the last FSX or FSR pulse Power-up will occur on the first FSX or FSR pulse The TRI-STATE PCM data output DX will remain in th S e high impedance state until the second FSX pulse YNCHRONOUS OPERATION For synchronous operation the same master clock and bit clock should be used for both the transmit and receive directions In this mode a clock must be applied to MCLKX and the MCLKR PDN pin can be used as a power-down control A low level on MCLKR PDN powers up the device M and a high level powers down the device In either case CLKX will be selected as the master clock for both the transmit and receive circuits A bit clock must also be applied to BCLKX and the BCLKR CLKSEL can be used to select the proper internal divider for a master clock of 1 536 t MHz 1 544 MHz or 2 048 MHz For 1 544 MHz operation he device automatically compensates for the 193rd clock W pulse each frame ith a fixed level on the BCLKR CLKSEL pin BCLKX will be selected as the bit clock for both the transmit and receive directions Table 1 indicates the frequencies of operation w C hich can be selected depending on the state of BCLKR mLKSEL In this synchronous mode the bit clock BCLKX ay be from 64 kHz to 2 048 MHz but must be synchronous with MCLKX E ach FSX pulse begins the encoding cycle and the PCM data from the previous encode cycle is shifted out of the enabled DX output on the positive edge of BCLKX After 8 bit clock periods the TRI-STATE DX output is returned to a high impedance state With an FSR pulse PCM data is latched via the DR input on the negative edge of BCLKX (or BCLKR if running) FSX and FSR must be synchronous with MCLT X R K ABLE I Selection of Master Clock Frequencies BCLKR CLKSEL Clocked 0 1 Master Clock Frequency Selected TP3057 2 048 MHz 1 536 MHz or 1 544 MHz 2 048 MHz TP3054 1 536 MHz or 1 544 MHz 2 048 MHz 1 536 MHz or 1 544 MHz ASYNCHRONOUS OPERATION For asynchronous operation separate transmit and receive clocks may be applied MCLKX and MCLKR must be 2 048 MHz for the TP3057 or 1 536 MHz 1 544 MHz for the TP3054 and need not be synchronous For best transmission performance however MCLKR should be synchronous with MCLKX which is easily achieved by applying only static logic levels to the MCLKR PDN pin This will automatically connect MCLKX to all internal MCLKR functions (see Pin Description) For 1 544 MHz operation the device automatiF cally compensates for the 193rd clock pulse each frame SX starts each encoding cycle and must be synchronous with MCLKX and BCLKX FSR starts each decoding cycle and must be synchronous with BCLKR BCLKR must be a clock the logic levels shown in Table 1 are not valid in asynchronous mode BCLKX and BCLKR may operate from S 64 kHz to 2 048 MHz HORT FRAME SYNC OPERATION The COMBO can utilize either a short frame sync pulse or a long frame sync pulse Upon power initialization the device assumes a short frame mode In this mode both frame sync pulses FSX and FSR must be one bit clock period long w ith timing relationships specified in Figure 2 With FSX high during a falling edge of BCLKX the next rising edge of BCLKX enables the DX TRI-STATE output buffer which will output the sign bit The following seven rising edges clock out the remaining seven bits and the next falling edge disables the DX output With FSR high during a falling edge of BCLKR (BCLKX in synchronous mode) the next falling edge of BCLKR latches in the sign bit The following seven falling edges latch in the seven remaining bits All four devices may utilize the short frame sync pulse in synchronous or L asynchronous operating mode ONG FRAME SYNC OPERATION F To use the long frame mode both the frame sync pulses wSX and FSR must be three or more bit clock periods long ith timing relationships specified in Figure 3 Based on the transmit frame sync FSX the COMBO will sense whether short or long frame sync pulses are being used For 64 kHz operation the frame sync pulse must be kept low for a minimum of 160 ns The DX TRI-STATE output buffer is enabled with the rising edge of FSX or the rising edge of BCLKX hichever comes later and the first bit clocked out is the sign bit The following seven BCLKX rising edges clock out the remaining seven bits The DX output is disabled by the falling BCLKX edge following the eighth rising edge or by FSX going low whichever comes later A rising edge on the receive frame sync pulse FSR will cause the PCM data at DR to be latched in on the next eight falling edges of BCLKR (BCLKX in synchronous mode) All four devices may utilize the long frame sync pulse in synchronous or asynchronous I mode n applications where the LSB bit is used for signalling with FSR two bit clock periods long the decoder will interpret the lost LSB as `` '' to minimize noise and distortion
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