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Part: EA-C9
Category:
ASICs
-> Gate Array
Description: 3.3-volt, 0.35-micron (drawn) CMOS Embedded Array
Company: NEC Electronics Inc.
Datasheet: Download EA-C9 datasheet File size : 124 kB
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NEC Electronics Inc.
Preliminary
EA-C9 3.3-Volt, 0.35-Micron (drawn) CMOS Embedded Array
March 1997
Description
NEC's high-performance 0.35 µm drawn (0.27 µm L-effective) EA-C9 embedded array family offers both support for embedded high-density macros as well as the short turnaround time of a gate array resulting in a timeto-market advantage. In this product, NEC combines high-performance CMOS gate array primitives with diffused, embedded blocks such as RAM and ROM. EA-C9 features 2- and 3- level metal CMOS technology with an extensive family of interface macros to support very high-speed system clocks such as GTL, GTL+, HSTL, and pECL. PCI signaling standards are also supported including 3.3V 66 MHz PCI. This technology is enhanced by a set of advanced features including phase-locked loops, clock tree synthesis, and high-speed memory. The EA-C9 embedded array family of 3.3V devices consists of 18 masters, offered in densities of 190K raw gates to 1.5 million raw gates. Usable gates range from 76K to 927K used gates. As the EA-C9 ASIC family follows basically a gate array approach, it offers short turnaround times for silicon processing and lower development costs compared to cell-based ASICs. The turnaround time is kept short by fixing the embedded core locations and beginning prototype fabrication in parallel with place and route design steps.
Figure 1. Embedded Array Core Integration
Gate Array I/O Cells
High Density Memory
High Density Cell-Based Compiled Memory
High Density Memory
Log ic Fun ctio n
Gate Array Primitives (Sea-of-Gate)
Gate Array Base Master
Applications
The EA-C9 family is ideal for applications where high density is mandatory and a short time-to-market path is required. For example, RAM-dominated designs can be realized with reduced die size and a reasonable turnaround time. EA-C9 is well-suited for designs that may require rework, because the logic function portion of the design uses gate array primitives created just by the final metal masks. Typical applications include engineering workstations, telecommunications systems, advanced graphics and low power applications where very high performance is required.
Table 1. EA-C9 Series Features and Benefits
EA-C9 Series Features · · · · · · · · · · · · · · 0.35 µm (drawn) 2- and 3-level metal CMOS technology Advanced embedded array architecture Eighteen base arrays with raw gates from 190K to 1.5M Narrow pad pitch for maximum gate to pad ratio Pad counts from 300 to 1060M GTL, GTL+, pECL, and all four classes of HSTL Full range of 5V-protected I/O buffers PCI buffers including 3.3V 66 MHz PCI buffer Digital Phase-Locked Loop (DPLL) macros Low power dissipation: 0.9 µW/MHz/gate Extensive package offering: PQFP, TQFP, BGA, TAB Clock Tree Synthesis tool automates clock tree design Floorplanner supplies layout information for resynthesis Popular, third-party CAE tools supported EA-C9 Series Benefits Delivers dense cell structure and high speed Enables fast TAT and dense memories Provides many base sizes to give best fit to design needs Minimizes device cost Support high I/O integration and wide system bus widths Interfaces to high speed memory and processor buses Allows interface with 5V logic while protecting 3.3V ASIC Supports signaling methods defined in the PCI Specification Eliminates clock insertion delay, reduces total clock skew Provides low power consumption at high system clock rates Delivers customer-specific package requirements Minimizes on-chip clock skew for high performance Reduces design time and improves device performance Enables a smooth flow from customer design to silicon
OpenCAD is a registered trademark of NEC Electronics Inc. All non-NEC trademarks are the property of their respective owners.
A12633EU1V0DS00
EA-C9
Array Architecture
The EA-C9 gate array family is built with NEC's 0.35micron (drawn) channelless array architecture. As shown in Figure 2, the array is divided into I/O and core regions. The I/O region contains input and output buffers. The core region contains the sea-of-gates array and embedded blocks. The EA-C9 gate arrays architecture provides extra flexibility for high performance system designs. As shown in Figure 2, the arrays contain two power rails: a 3.3V rail, and a second power rail (VDD2) for special I/O types. The VDD2 rail is used for interfaces such as HSTL where a very low I/O power supply is required (1.4 to 1.6V). All four classes of HSTL buffer are supported. The VDD2 rail may be separated into sections to allow one device to support two or more buses requiring special I/O voltages. Examples of spread I/O cells that may use this VDD rail are HSTL and 5V PCI. Each section can operate as an independent voltage zone, and sections can be linked together to form common voltage zones.
3.3V VDD Rail VDD2
P-Channel N-Channel
Figure 2. Power Rail Structure
Core Region
Core Region
Drawing not to scale
The core region consists of an array of gates. Each gate contains 2 n-channel and 2 p-channel MOS logic transistors. One core gate is equivalent to one 2-input NAND gate (L302). The logic transistors are sized to offer a superior ratio of speed to silicon area.
Table 2. EA-C9 Base Array Line-up
Device(1) (µPD654xx) 2LM 3LM Available Gates Usable Gates(2) 2LM 3LM Max Pads Reg. Tight Pitch Pitch
06 07 08 09 10 11 13 15 17
Notes:
26 27 28 29 30 31 33 35 37
190152 249948 317904 376740 462088 629824 805580 1076032 1545240
76061 99979 127162 150696 184835 251930 322232 430413 618096
114091 149969 190742 226044 277253 377894 483348 645619 927144
300 340 380 412 452 524 588 676 804
388 444 500 540 596 692 772 892 1060
The embedded array approach allows the combination of high-density cores with a prototype turnaround time equal to gate arrays. Embedded blocks such as RAM and ROM can be placed into the sea-of-gates area within the EA-C9 base master. The area used for these blocks is defined by pre-diffusion. The logical function is created by the final metalization masks. This enables the usage of a gate array master and digital macros from the cell-based technology CB-C9. Cores from the BiCMOS QB-9 family may also be embedded. Various kinds of memory macros are available for EA-C9. Designers can select either gate array memory compilers using gate array cells or cell-based compilers which offer higher density and faster access times. Cell-based type memory blocks are generated based on advanced memory compiler tools and thus ensure highest flexibility for design requirements. The available memory types are described in Table 3.
(1) 2LM represents two-layer metal; "3LM" represents three-layer metal. (2) Actual gate utilization varies depending on circuit implementation. Utilization is 40% for 2LM; 60% for 3LM.
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EA-C9
Table 3. EA-C9 Compiled Memory Types
Family CB-IC Type High-speed Mode Sync. Sync. High-density G/A Sync. Async. Async. Ports Word Size 1 2 1 1 2 1-32 bits 1-32 bits 1-32 bits 2-128 bits 2-128 bits Max. Size 32-2K words 8-word incr. 32-2K words 8-word incr. 32-2K words 1-word incr. 2-1K words 2-word incr. 2-1K words 2-word incr.
support for 160 MHz) for chip-to-chip skew minimization and Clock Tree Synthesis (CTS). CTS -- supported by an NEC proprietary design tool -- is used for clock skew management through the automatic insertion of a balanced buffer tree. The clock tree insertion method minimizes large-capacitive trunks and is especially useful with the hierarchical, synthesized design style being used for high-integration devices. RC values for actual net lengths of the clock tree are used for back annotation after place and route operations. A skew as low as ±100 ps can be achieved. A c c u r a t e Design Verification. Nonlinear timing calculation is a very important requirement of the highdensity, deep sub-micron ASIC designs. NEC makes use of the increased accuracy delivered by the nonlinear table l o o k - u p delay calculation methodology and offers consistent wire load models to ensure a high accuracy of the design verification. Design Rule Check. A comprehensive design rule check (DRC) program reports design rule violations as well as chip utilization statistics for the design netlist. The generated report contains such information as net counts, total pin and gate counts, and utilization figures. Layout. During design synthesis, wire load models are used to get delay estimations in a very early state of the design flow. In general, there's no need for customers to perform the floorplanning to meet the required timing. During layout, enhanced in-place optimization (IPO) features of the layout tools and engineering change order (ECO) capabilities of the synthesis tools are used to optimize critical timing paths defined by the given timing constraints. This feature can reduce the total design time.
Packaging and Test
EA-C9 gate arrays support automatic test generation through a scan-test methodology, which allows higher fault coverage, easier testing and quicker development time. NEC also offers optional BIST test structures for RAM testing. NEC offers advanced packaging solutions including Tape Ball Grid Arrays (TBGA), Ball Grid Arrays (BGA), Plastic Ball Grid Arrays (PBGA), Plastic Quad Flat Packs (PQFP), Low Profile Plastic Quad Flat Packs (LQFP), Thin Plastic Quad Flat Packs (TQFP), and Pin Grid Arrays (PGA). Please call your local NEC ASIC Design Center for a listing of available master/package combinations.
CAD Support
The EA-C9 family is fully supported by NEC's sophisticated OpenCAD® design framework, EA-C9 maximizes design quality and flexibility while minimizing ASIC design time. NEC's OpenCAD system allows designers to combine the EDA industry's most popular third-party design tools with proprietary NEC tools, including those for advanced floorplanner, clock tree synthesis, automatic test pattern generation (ATPG), full-timing simulation, accelerated fault grading and advanced place and route algorithms. The latest OpenCAD system is open for sign-off using standard EDA tools. NEC offers RTL- and STA- (Static Timing Analysis) sign-off procedures to shorten the ASIC design cycle of high-complexity designs. Support of High-Speed Systems. High-speed systems require tight control of clock skew on the chip and between devices on a printed circuit board. EA-C9 provides two features to control clock skew: the Digital PLL (DPLL) working at frequencies up to 100 MHz (with planned
Test Support
The EA-C9 family supports automatic test generation through a scan test methodology. It includes internal scan, boundary scan (JTAG) and built-in-self-test (BIST) architecture for easy and high-performance production RAM testing. This allows higher fault coverage, easier testing and faster development time.
Supplemental Publications
This data sheet contains preliminary specifications and operational data for the EA-C9 embedded array family. Additional information is available in NEC's EA-C9 Design Manual, Block Library, Memory Macro Design Manual and other related documents. Please call your local NEC design center for additional information; see the back of this data sheet for locations and telephone numbers.
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EA-C9
Absolute Maximum Ratings
Power supply voltage, VDD Input Voltage, VI 3V Input buffer (at VI 1 A (typ) -40 to +85°C -65 to +150°C -0.5 to 4.6 V -0.5 to 4.6 V -0.5 to 6.6 V Input Output I/O -0.5 to +4.6 V
Input/Output Capacitance
VDD = VI = 0 V; f = 1 MHz Terminal 3V 5V 3V 5V 3V 5V Symbol CIN COUT CI/O Min 4.0 8.0 4.0 8.0 4.0 8.0 Typ Max 6.0 10.0 6.0 10.0 6.0 10.0 Unit pF pF pF
(1) Values include package pin capacitance.
Power Consumption
Description Internal gate Input buffer (FI01) Output buffer (FO01 @ 15 pF) Limits 1.09 15.05 234 Unit µW/MHz µW/MHz µW/MHz
Caution: Exposure to absolute maximum ratings for extended periods may affect device reliability; exceeding the ratings could cause permanent damage. T h e device should not be operated outside the recommended operating conditions.
Recommended Operating Conditions
3.3V Interface Block Parameter I/O Power supply voltage Junction temperature High-level input voltage Low-level input voltage Positive trigger voltage Negative trigger voltage Hysteresis voltage Input rise/fall time Input rise/fall time, Schmitt Symbol VDD TJ VIH VIL VP VN VH tR, tF tR, tF Min 3.0 -40 2.0 0 1.5 0.6 1.1 0 0 Max 3.6 +125 VDD 0.8 2.7 1.4 1.5 200 10 5V Interface Block Min 3.0 -40 2.0 0 2.2 0.84 1.36 0 0 Max 3.6 +125 5.5 0.8 2.55 1.01 1.54 200 10 5V PCI Level Min 3.0 -40 2.0 0 -- -- -- 0 -- Max 3.6 +125 VCC 0.8 -- -- -- 200 -- 3.3V PCI Level Min 3.0 -40 0 . 5 VC C 0 -- -- -- 0 -- Max 3.6 +125 VCC 0 . 3 VC C -- -- -- 200 -- Unit V °C V V V V V ns ns
AC Characteristics
VDD = 3.3V ± 0.3V; Tj = -40 to +125°C Parameter Toggle frequency (D-flip-flop) Delay time, 2-input NAND gate @ 5V Standard gate (F302) tPD tPD 99 150 84 119 ps ps ps ps F/O = 1; L = 0 mm F/O = 2; L = 0.5 mm F/O = 1; L = 0 mm F/O = 2; L = 0.5 mm Symbol fTOG Min Typ Max 670 Unit MHz Conditions F/O = 2, 5V
Power gate (F322) Delay time, buffer Input buffer (FI01) Input buffer (FI01) Output buffer (FO01) Output rise time (FO01) Output fall time (FO01)
tPD tPD tPD tR tF
188 216 1.40 2.35 1.83
ps ps ns ns ns
F/O = 1; L = 0.5 mm F/O = 2; L = 0 mm CL = 15 pF CL = 15 pF CL = 15 pF
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EA-C9
DC Characteristics
VDD = 3.3V ± 0.3V; Tj = -40 to +125°C Parameter Quiescent current (µPD654xx) (1) -19, -39 -17, -37, -15, -35, -13, -33, -11, -31 -10, -30, -09, -29, -08, -28 -06, -26, -07, -27 Off-state output leakage current 3V output buffer 5V-protected TTL buffer Output short circuit current (3) Input leakage current (2) Regular 50 k pull-up 5 k pull-up 50 k pull-down Resistor values 50 k pull-up (4) 5 k pull-up 50 k pull-down Low-level output current (5V Interface Block) 1 mA 2 mA 3 mA 6 mA 9 mA 12 mA High-level output current (5V Interface Block) 1 mA 2 mA 3 mA 6 mA 9 mA 12 mA Low-level output current (3.3V Interface Block) 3 mA (FO09) 6 mA (FO04) 9 mA (FO01) 12 mA (FO02) 18 mA (FO03) 24 mA (FO06) High-level output current (3.3V Interface Block) 3 mA (FO09) 6 mA (FO04) 9 mA (FO01) 12 mA (FO02) 18 mA (FO03) 24 mA (FO06) Low-level output voltage High-level output voltage Symbol IL IL IL IL IOZ IOZ IOS II II II II Rpu Rpu Rpu IOL IOL IOL IOL IOL IOL IOH IOH IOH IOH IOH IOH IOL IOL IOL IOL IOL IOL IOH IOH IOH IOH IOH IOH VOL VOH ±104 89 654 79 37.1 5.0 41.9 Min Typ 70 40 20 10 Max 1400 800 400 200 ±10 ±10 -250 ±10 165 1305 141 83.1 10.6 105.8 TBD TBD TBD TBD TBD TBD Unit µA µA µA µA µA µA mA µA µA µA µA k k k mA mA mA mA mA mA mA mA mA mA mA mA 10 20 30 40 60 75 mA mA mA mA mA mA mA mA mA mA mA mA V V VOL = 0.4 V VOL = 0.4 V VOL = 0.4 V VOL = 0.4 V VOL = 0.4 V VOL = 0.4 V VOH = 2.4 V VOH = 2.4 V VOH = 2.4 V VOH = 2.4 V VOH = 2.4 V VOH = 2.4 V VOL = 0.4 V VOL = 0.4 V VOL = 0.4 V VOL = 0.4 V VOL = 0.4 V VOL = 0.4 V VOH = 2.4 V VOH = 2.4 V VOH = 2.4 V VOH = 2.4 V VOH = 2.4 V VOH = 2.4 V IOL = 0 mA IOH = 0 mA Conditions VI = VDD or GND VI = VDD or GND VI = VDD or GND VI = VDD or GND VO = VDD or GND VO = VDD or GND VO = GND VI = VDD or GND VI = GND VI = GND VI = VDD
36 284 28 21.8 2.8 25.6 1 2 3 6 9 12 -1 -1 -3 -3 -3 -3 3 6 9 12 18 24 -3 -6 -9 -12 -18 -24
0.1 V DD-0.1
Notes: (1) Static current consumption increases if an I/O block with on-chip pull-up/ pull-down resistor or an oscillator is used. Contact an NEC ASIC Design Center for assistance in calculation.
(2) Leakage current is limited by tester capabilities. Specification listed represents this measurement limitation. Actual values will be significantly lower. (3) Rating is for only one output operating in this mode for less than 1 second. (4) Resistor is called 50k for backwards compatibility.
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