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Part: M10059EJ7V0DSJ1
Category:
Memory
-> Line Buffer
Description:
Company: NEC Electronics Inc.
Datasheet: Download M10059EJ7V0DSJ1 datasheet File size : 57 kB
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Datasheet text preview:
DATA SHEET
MOS INTEGRATED CIRCUIT
µP D 4 8 5 5 0 5
LINE BUFFER 5K-WORD BY 8-BIT
Description
The µPD485505 is a 5,048 words by 8 bits high speed FIFO (First In First Out) line buffer. Its CMOS static circuitry provides high speed access and low power consumption. The µPD485505 can be used for one line delay and time axis conversion in high speed facsimile machines and digital copiers. Moreover, the µPD485505 can execute read and write operations independently on an asynchronous basis. Thus the µPD485505 is suitable as a buffer for data transfer between units with different transfer rates and as a buffer for the synchronization of multiple input signals. There are three versions, E, K, P, and L. This data sheet can be applied to the version P and L. These versions operate with different specifications. Each version is identified with its lot number (refer to 7. Example of Stamping).
Features
· 5,048 words by 8 bits · Asynchronous read/write operations available · Variable length delay bits; 21 to 5,048 bits (Cycle time: 25 ns) 15 to 5,048 bits (Cycle time: 35 ns) · Power supply voltage VCC = 5.0 V ± 0.5 V · Suitable for sampling one line of A3 size paper (16 dots/mm) · All input/output TTL compatible · 3-state output · Full static operation; data hold time = infinity
Ordering Information
Part Number R/W Cycle Time 25 ns 35 ns Package 24-pin plastic SOP (11.43 mm (450))
µP D 4 8 5 5 0 5 G - 2 5 µP D 4 8 5 5 0 5 G - 3 5
The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. M10059EJ7V0DSJ1 (7th edition) Date Published December 2000 N CP(K) Printed in Japan
The mark
shows major revised points.
©
1994,1996
µPD485505
Pin Configuration (Marking side)
24-pin plastic SOP (11.43 mm (450)) [µP D 4 8 5 5 0 5 G ]
DOUT0 DOUT1 DOUT2 DOUT3 RE RSTR GND RCK DOUT4 DOUT5 DOUT6 DOUT7
1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20 19 18 17 16 15 14 13
DIN0 DIN1 DIN2 DIN3 WE RSTW VCC WCK DIN4 DIN5 DIN6 DIN7
D IN0 - DIN7 WCK RCK WE RE RSTW RSTR V CC GND
: Data Inputs : Write Clock Input : Read Clock Input : Write Enable Input : Read Enable Input : Reset Write Input : Reset Read Input : +5.0 V Power Supply : Ground
D OUT0 - DOUT7 : Data Outputs
Remark Refer to 5. Package Drawing for the 1-pin index mark.
2
Data Sheet M10059EJ7V0DS00
µPD485505
Block Diagram
VCC GND
WCK
Write Address Pointer
RSTW RE
DIN0 DIN1 DIN2 DIN3 DIN4 DIN5 DIN6 DIN7 Memory Cell Array 40,384 bits (5,048 words by 8 bits)
Output Buffer Input Buffer
DOUT0 DOUT1 DOUT2 DOUT3 DOUT4 DOUT5 DOUT6 DOUT7
WE RSTR Read Address Pointer RCK
Data Sheet M10059EJ7V0DS00
3
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