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Details, datasheet, quote on part number:QB-8
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Datasheet text preview:
NEC Electronics Inc.
Preliminary
Description
N E C ' s 3.3-volt QB-8 family consists of ultra-highp e r f o r m a n c e , submicron gate arrays targeted for a p p l i c a t i o n s requiring high speeds and low power dissipation. The QB-8 family offers not only high speed but also low power dissipation and high density at a reasonable price. This combination of features is made possible through the use of a unique epi-less process that delivers the low cost and short manufacturing time of CMOS with the high speed of bipolar technology. QB-8 is targeted for designs in advanced networks and data communications, industrial applications, telecomm u n i c a t i o n s , and computing applications such as engineering workstations, high-end personal computers, mainframes, and high-speed peripherals. The device processing includes a 0.44-micron silicongate technology and three-layer metalization. This t e c h n o l o g y features channeless (sea-of-gate) architecture with an internal gate delay of 107 ps (F/O = 1, L = 0) and power dissipation of 1.0 µW/MHz/gate. The high-performance I/O macros include LVTTL, GTL, HSTL, and pECL. PCI signaling standards are also supported, including those for a 3.3-volt, 66 MHz PCI. T h i s technology is enhanced by a set of advanced features that include phase-locked loops, clock tree synthesis, and high-speed memories.
QB-8 3.3-Volt, 0.44-Micron Gate Arrays
April 1996
Figure 1. 672-pin BGA
T h e QB-8 family consists of 11 masters offered in densities of 33K to 382K raw gates. The gate array f a m i l y is supported by NEC's OpenCAD® design system, a mixture of popular third-party CAE tools, and proprietary NEC tools. NEC's proprietary tools include the GALET floorplanner, which helps reduce design cycle time and improve design performance, clock tree synthesis for clock skew minimization, and a table lookup delay calculator for accurate delay calculation.
Table 1. QB-8 Series Features and Benefits
QB-8 Series Features · 0.44-micron (drawn), 3-level metal process · BiCMOS process does not use epitaxial layer · 11 base arrays with raw gates from 33K to 382K gates · Optimized pad pitch · Optimized I/O cell size · "PUZZLE" cell architecture with mixed transistor sizes · PCI, GTL, HSTL, pECL interface blocks · 90- to 160-MHz PLL and clock tree synthesis · Clock tree synthesis tool · Low power dissipation of 1.0 µW/MHz/gate · Asynchronous 1- and 2-port RAM blocks · BGA, PQFP, PGA packaging · 622-MHz I/O and 622MHz PLL in QB-8E (release FY/96) QB-8 Series Benefits · Delivers Bipolar speed at CMOS turn-time and cost · Shortens turnaround time and reduces cost of production · Satisfies user requirements with many base arrays · Reduces assembly cost for BGA and QFP wirebond · Enables high-speed I/O buffers in only one I/O slot · Achieves high speed; keeps driveability and low power · Delivers I/O for up to 250-MHz data transfer · Eliminates clock insertion delay; reduces clock skew · Automatic insertion of low-skew clock tree · Delivers support for ultra-high-speed communications · Allows high-speed, low-power BiCMOS operation · Provides support for high-speed RAM · Supports popular packaging solutions
A11111EU1V0DS00
OpenCAD is a registered trademark of NEC Electronics Inc.
QB-8
Array Architecture
T h e QB-8 family is built with NEC's 0.44-micron channeless array architecture. The array is divided into I/O and core regions (see Figure 2). The I/O regions c o n t a i n input and output buffers. The core region contains the sea-of-gates array. The QB-8 gate arrays architecture provides extra flexibility for high-performance system designs. The arrays contain several power rails, a 3.3-volt rail, and power rails for special I/O types such as 5-volt PCI, HSTL, GTL, and pECL.
3.3V
Figure 2. Chip Layout and Internal Cell Configuration
Core Architecture
QB-8 uses a proprietary architecture called PUZZLE. It combines three transistors of different sizes into a single, highly dense architecture tightly interlocked as in a puzzle. The result is an ASIC that uses small C M O S transistors for low input capacitance and signaling within a macro, and bipolar transistors for high drive-ability and signaling between macros. The core region consists of an array of gates. Each c e l l contains four n-channel and two p-channel t r a n s i s t o r s and one bipolar transistor. One cell is equivalent to one 2-input NAND gate (L302). The logic transistors are sized to offer a superior ratio of speed to silicon area.
Universal power lines
Gate Array Sizes
Device µPD67821 µPD67822 µPD67823 µPD67824 µPD67825 µPD67826 µPD67827 µPD67828 µPD67829 µPD67830 µPD67831 Available Gates 32832 44352 56800 69520 93184 123808 136752 167280 234320 292896 381840 Usable Gates 22982 31046 39760 48664 65229 86666 95726 117096 164024 205027 267288 I/O Pads 156 180 204 224 260 300 316 348 412 460 524 Metal Layers 3 3 3 3 3 3 3 3 3 3 3
Test
The QB-8 family supports automatic test generation through a scan-test methodology, which allows higher fault coverage, easier testing, and quicker development time. NEC also offers optional BIST test architecture for RAM testing.
Packaging
NEC offers an extensive variety of more than 60 package types. The QB-8 family can be packaged in NEC's most p o p u l a r surface-mount and through-hole packages. These include plastic quad-flat packs (PQFPs). Pin grid arrays (PGAs) and BGA packages are also supported. The 672-pin BGA package is shown in Figure 1.
Publications
T h i s data sheet contains specifications, package information, and operational data for the QB-8 gate array families. Additional design information is available in NEC's QB-8 Block Library and QB-8 Design Manual. Call your local NEC design center or call the NEC toll-free literature line for additional ASIC design i n f o r m a t i o n ; see the back of this data sheet for locations and telephone numbers.
Actual gate utilitization varies depending on circuit implementation. Utilization is 70% for three-layer metal. Depending on package and circuit s p e c i f i c a t i o n s , some pads are used for VDD and GND and are not available as signal pads.
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QB-8
Absolute Maximum Ratings
Power supply voltage, VDD Input voltage, VI 3 V input buffer (at VI 1 A (typ) 40 to +85°C 65 to +150°C 0.5 to 4.6 V 0.5 to 4.6 V 0.5 to 6.6 V 0.5 to 4.6 V
Input/Output Capacitance
VDD = VI = 0 V; f = 1 MHz Terminal Input Output I /O Symbol CIN COUT CI / O Typ 10 10 10 Max 20 20 20 Unit pF pF pF
Note: (1) Values do not include package pin capacitance.
Power Consumption
Description Internal cell Input block (FI01) Output block (F002 @ 15 pF) Limits 1.09 6.92 260 Unit µW/MHz µW/MHz µW/MHz
Recommended Operating Conditions
3 V Buffer Parameter Power supply voltage Junction temperature Low-level input voltage High-level input voltage Input rise or fall time Input rise or fall time, Schmitt Symbol V DD TJ VIL VIH tR, tF t R, tF Min 3.0 40 0 2.0 0 0 Max 3.6 +125 0.8 V DD 200 10 5 V-Tolerant Min 3.0 40 0 2.0 0 0 Max 3.6 +125 0.8 V DD 200 10 3.3 V PCI Min 3.0 40 0.5 0.5 VDD 0 0 Max 3.6 +125 0.3 VDD VDD+0.5 200 200 ns 5 V PCI Min 3.0 40 0.5 2.0 0 -- Max 3.6 +125 0.8 V D D+ 0 . 5 200 -- Unit V °C V V ns ms
AC Characteristics
VDD = 3.3 V ± 0.3 V; Tj = -40 to +125°C Parameter Toggle frequency Delay time 2-input NAND (F322) Flip-flop (F611) tPD tPD tPD tPD tSETUP tHOLD Input buffer (FI01) Output buffer (12 mA) 3.3 V Output buffer (12 mA) 3.3 V Output buffer (12 mA) 5 V-tolerant Output buffer (6 mA) 5 V-tolerant Output buffer (6 mA) 5 V-tolerant Output rise time (9 mA) Output fall time (9 mA) tPD tPD tPD tPD tPD tPD tPD tR tF 540 10 211 220 925 2136 TBD 1004 2158 920 680 90 106 463 492 ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps F/O = 1; L = 0 mm F/O = 2; L = typ F/O = 1; L = 0 mm F/O = 2; L = typ -- -- F/O = 1; L = 0 mm F/O = 2; L = typ CL = 0 pF CL = 50 pF CL = 0 pF, 50 pF CL = 0 pF CL = 50 pF CL = 15 pF CL = 15 pF Symbol f TOG Min 670 Typ Max Unit MHz Conditions D-F/F; F/O = 1
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