|Category||ASICs => Gate Array|
|Description||Mixed-voltage 0.6-micron CMOS Gate Arrays|
|Company||NEC Electronics Inc.|
|Datasheet||Download UNIVERSALPCISeries datasheet
UNIVERSAL PCI SERIES MIXED-VOLTAGE 0.6-MICRON CMOS GATE ARRAYS
NEC's Universal PCI Series gate array family provides designers with the flexibility and performance required to develop devices for mixed-voltage systems. NEC combines the highest performance 0.6-micron 2- and 3level metal CMOS technology with an extremely versatile I/O structure which supports high-speed interface specifications such as 5V PCI, 3.3V PCI, Universal PCI and GTL. This technology is enhanced by a set of advanced features including voltage level shifting circuits, voltage level sense circuits, phase-locked loops, clock tree synthesis, and high-speed compiled memory. The gate array family is supported by a mixture of popular thirdparty CAE tools, and proprietary NEC tools.
The features delivered in the Universal PCI Series are vital for successful mixed-voltage, high-speed designs for personal computers, engineering workstations and mobile systems. The Universal PCI Series gate array family is of special interest to designers facing complex choices in mixedvoltage system architecture. With its ability to support both 3.3V and 5V signalling in one I/O cell, NEC's Univesal PCI Series eliminates the risk of predicting when systems will crossover from to 3.3V. Designers can use the unique features of this family to develop one device which supports both low-end and high-end systems; both 5V and 3.3V systems. During the prototype phase, this strategy saves design development time and budget. During the production phase, it stabilizes and reduces inventory complexity.
Universal PCI Series Features 0.6-micron, 2- and 3-level metal CMOS technology 14 base arrays with raw gates from to 210K; usable gates from to 157K, max pads from to 676 Standard and slew-rate controlled I/O with variable output drives: and mA in one I/O slot Universal PCI buffer, 5V PCI buffer, 3.3V PCI buffer, TTL, LVTTL, CMOS interfaces available, GTL in development Level Shift Circuits in each I/O Cell Level Sensing Circuit Macrocells Phase-Locked Loop (DPLL) macros in development Clock Tree Synthesis tool automates clock tree design High-speed, 1- and 2-port asynchronous RAM compiler Library characterized ± 5% and = 0-100°C Narrow pad pitch for maximum gate to pad ratio Popular, third-party CAE tools mixed with proprietary, powerful NEC tools, such as Floorplanner and ATPG
Universal PCI Series Benefits Delivers high-performance, dense array technology Provides a wide range of array sizes for the right mix of gate and pad count for various applications Provides multiple choices of drive strength for optimal fit of buffer strength to application Flexible interfaces support a wide range of industrystandard, high-speed, low-noise specifications Each I/O is programmable for 5V or Universal signallin g Provides automatic sensing of Universal Vdd voltage and controls signalling level of Universal I/O buffers Eliminates clock insertion delay and minimizes chip-to-chip clock skew by synchronizing reference clock to chip chip Minimizes on-chip clock skew across large networks Optimizes RAM configuration and area Targets designs for use in high-performance systems Reduces pad-limited designs and saves silicon area Supports designer's preferred environment while delivering optimized NEC-specific CAE functions
The Universal PCI Series gate arrays architecture provides a great amount of flexibility for mixed-voltage system designs. As shown in Figure 2, the arrays contain three power rails: a 5V rail, a 3.3V rail, and a "Universal Rail." I/O operating off the Universal Rail are called Universal Buffers and are able to switch between 5V and 3.3V operation. The Universal PCI buffer used on Universal PCI Cards is one application for this capability. When Universal PCI I/O are used, the ASIC provides 5V PCI signalling when the card plugs into a 5V PCI bus, and 3.3V PCI signalling when the card plugs into a 3.3V PCI bus. NEC's level sense circuit may be used to determine the voltage level of the Universal Vdd rail and control the I/O to provide the appropriate signalling. The Universal Rail is divided into eight sections. Each section can operate as an independent voltage zone, and sections can be linked together to form common voltage zones. Overall, designs using this unique system can contain to 10 independent voltage zones.
NEC's voltage sensing circuit may be placed in each independent zone to determine the voltage level of the Universal voltage rail. In addition to the voltage sense circuit, each I/O buffer contains a voltage shift circuit to provide ensure appropriate voltage levels between the external signal, the buffer and the core.
The Universal PCI Series is built with NEC's 0.6-micron (drawn) channelless array architecture. As shown in Figure 2, the array is divided into I/O and core regions. The I/O region contains input and output buffers. The core region consists of an array of gates. Each gate contains 2 n-channel and 2 p-channel MOS logic transistors, and 4 small n-channel transistors for building compact RAM blocks. One core gate is equivalent to one 2-input NAND (L302). The logic transistors are sized to offer a superior ratio of speed to silicon area.
(1) Types A, and B differ in the number of Vdd rails and the number of pads available for I/O signals. Type A designs use all three Vdd rails (5V, 3.3V and Universal). Type B designs use the 5V and Universal Vdd rails. (2) In this family, input buffer pre-buffers are located in the I/O region and do not use any core gates. Actual gate utilization varies depending on circuit implementation. Utilization is 60% for 2LM; 75% for 3LM. (3) This column lists the number of signal pads for Type B designs. Type A designs will have four (4) fewer signal I/O than Type B. These four I/O will be used for the 3.3V power rail.
This data sheet contains preliminary specifications, package information, and operational data for the Universal PCI Series. Contact your local NEC Design Center or the NEC Literature Center for further ASIC design information; see the back of this data sheet for locations and phone numbers.
Power supply voltage, VDD Input/output voltage, / VO Latch-up current, ILATCH Operating temperature, TOPT Storage temperature, TSTG V to VDD >1 A (typ) to +150°CVDD = 1 MHz Terminal Input Output I/O Symbol CIN COUT CI/O Typ TBD Unit pF
Caution: Exposure to absolute maximum ratings for extended periods may affect device reliability; exceeding the ratings could cause permanent damage. The device should not be operated outside the recommended operating conditions.
Description Internal gate (1) Input buffer (FI0155) Output buffer @ 15 pF) Limits 17.8 623 Unit µW/MHz
5V CMOS Level Parameter I/O Power supply volt. Ambient temperature Low-level input volt. High-level input volt. Input rise/fall time Input rise/fall time, Schmitt Pos. Schmitt-trigger volt. Neg. Schmitt-trigger volt. Hysteresis volt. Symbol DD TA VIL VIH tR, tF tR, VN VH Min 0.7V DD Max DD 5V TTL Level Min Max DD 5V PCI Level Min Max 200 3.3V LVTTL Level Min TBD Max 200 1.0 TBD 3.3V PCI Level Min CC 0 Max CC 200 Unit µs V
VDD to +100°C Parameter Toggle Frequency Delay time, 2-input NAND gate @ 5V Standard gate (F302) tPD ps F/O 0 mm F/O 0.5 mm F/O 0 mm F/O 0.5 mm Symbol fTOG Min 274 Typ Max Unit MHz Conditions F/O 2, 5V
Power gate (F322) Delay time, buffer Input @ 5V Input @ 3.3V Output @ 5V Output @ 3.3V Output rise time @ 5V Output fall time @ 5V Output rise time @ 3.3V Output fall time @ 3.3V
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