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Details, datasheet, quote on part number:UPD16314GJ-001-8EU
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Datasheet text preview:
DATA SHEET
MOS INTEGRATED CIRCUIT
µ PD16314
DOT CHARACTER VFD CONTROLLER/DRIVER
DESCRIPTION
The µ PD16314 is a VFD controller/driver capable of displaying a dot matrix VFD. It has 80 anode outputs and 24 grid outputs. A single µ PD16314 can display up to 16C x 2L, 20C x 2L, or 24C x 2L. The µ PD16314 has character generator ROM in which 248 x 5 x 8 dot characters are stored.
FEATURES
· Dot matrix VFD controller/driver · Capable of driving anodes for cursor display (48 units) · 80 x 8 bits display RAM incorporated · Capable of alphanumeric and symbolic display through internal ROM (5 by 8 dots) 240 characters plus 8 user-defined characters · Display contents 16 columns by 2(1) rows + 32(16) cursors, 20 columns by 2(1) rows + 40(20) cursors, or 24 columns by 2(1) rows + 48(24) cursors. · Parallel data input/output (switchable between 4 bits and 8 bits) or serial data input/output can be selected. · On-chip oscillator · Custom ROM supported
ORDERING INFORMATION
Part Number Pac k age 144-PIN PLASTIC LQFP(FINE PITCH)(20x20), Standard ROM (ROM code: 001) 144-PIN PLASTIC LQFP(FINE PITCH)(20x20), Standard ROM (ROM code: 002)
µ PD16314GJ-001-8EU µ PD16314GJ-002-8EU
The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability and additional information.
Document No. S13231EJ1V0DS00 (1st edition) Date Published March 2000 NS CP(K) Printed in Japan
The mark · shows major revised point.
©
1997
2 Remark
TESTOUT OSCIN OSCOUT XOUT SDO SLK /CL LE 3 OSCILATIOR ADDRESS COUNTER 7 8 I/O B U F F E R INSTRUCTION REGISTER 7 8 INSTRUCTION DECORDER DISPLAY DATA RAM (DDRAM) 80 x 8 bits 8 CURSOR BLINK CONTROL CIRCUIT 8 4 7 CHARACTER GENERATOR DB4 to DB7 4 RAM (CGRAM) 8 x 5 x 8 bits 8 CHARACTER GENERATOR ROM (CGROM) 248 x 5 x 8 bits ANODE SIGNAL DRIVER 80 /RESET RESET CIRCUIT 5 MPU DS0 DS1 DLS R,L1 R,L2 PARALLEL TO SERIAL DATA CONVERTER 80-BIT SHIFT REGISTER 5 80-BIT LATCH 80 80 A1 to A80 7 7 TIMING GENERATOR 24 24-BIT SHIFT REGISTER 24 GRID SIGNAL DRIVER 24 G1 to G24
1. BLOCK DIAGRAM
/xxx indicates active low signals.
TEST
IM
/CS
RS,STB
Data Sheet S13231EJ1V0DS00
R,/W(/WR)
E(/RD),SCK
8
DATA REGISTER
8
SI,SO
DB0 to DB3
µ PD16314
VDD1
VDD2
VSS1
VSS2
µ PD16314
2. PIN CONFIGURATION (Top View)
N.C. A71 A72 A73 A74 A75 A76 A77 A78 A79 A80 G24 G23 G22 G21 G20 G19 G18 G17 G16 G15 G14 G13 G12 G11 G10 G9 G8 G7 G6 G5 G4 G3 G2 G1 N.C.
108 109
A70 A69 A68 A67 A66 A65 A64 A63 A62 A61 A60 A59 A58 A57 A56 A55 A54 A53 A52 A51 A50 A49 A48 A47 A46 A45 A44 A43 A42 A41 A40 A39 A38 A37 A36 A35
73 72 144 1 37 36 N.C. A34 A33 A32 A31 A30 A29 A28 A27 A26 A25 A24 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 N.C.
Remark Use all power supply pins. Leave N.C. pins open.
VDD2 VSS2 VDD1 XOUT OSCOUT OSCIN /RESET TEST DLS DS1 DS0 R,/W(/WR) RS,STB E(/RD),SCK SI,SO DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 IM MPU /CS R,L1 R,L2 /CL LE SDO SLK TESTOUT VSS1 VSS2 VDD2
Data Sheet S13231EJ1V0DS00
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