|
Details, datasheet, quote on part number:UPD16857
| |
Datasheet text preview:
DATA SHEET
MOS INTEGRATED CIRCUIT
µPD16857
MONOLITHIC 6 channel H-BRIDGE DRIVER
DESCRIPTION
µPD16857 is monolithic 6 channel H-bridge driver employing power MOS FETs in the output stages. The MOS
FETs in the output stage lower the saturation voltage and power consumption as compared with conventional drivers using bipolar transistors. In addition, a low-voltage malfunction prevention circuit is also provided that prevents the IC from malfunctioning when the supply voltage drops. A 30-pin plastic shrink SOP package is adopted to help create compact and slim application sets. In the output stage H bridge circuits, two low-ON resistance H-bridge circuits for driving actuators, and another three channels for driving sled motors and tilt control, and another channel for driving loading motor are provided, making the product ideal for applications in DVD-ROM/DVD-RAM.
FEATURES
· Six H-bridge outputs employing power MOS FETs. · High speed PWM drive corresponding: Operating input frequency 120 kHz (MAX.) · Low voltage malfunction prevention circuit: Operating control block voltage under 2.5 V (TYP.) · Loading into 38-pin shrink SOP (300 mil).
ABSOLUTE MAXIMUM RATINGS (TA = 25 °C)
Parameter Control block supply voltage Output block supply voltage Input voltage Output current Power consumptionNote Peak junction temperature Storage temperature range Symbol VD D VM VI N ID ( p u l s e ) PT T CH(MAX) Tstg PW 5 ms, Duty 20 % Condition Rating 0.5 to +6.0 0.5 to +13.5 0.5 to VDD+0.5 ±1 . 0 1.0 150 55 to +150 Unit V V V A/ch W °C °C
Note
When mounted on a glass epoxy board (10 cm × 10 cm × 1 mm, 15 % copper foil)
The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. S13908EJ1V0DS00 (1st edition) Date Published July 1999 N CP(K) Printed in Japan
©
1999
µPD16857
RECOMMENDED OPERATING CONDITIONS
Parameter Control block supply voltage Output block supply voltage Output current (pulse) Operating frequency Operating temperature range Peak junction temperature Symbol VD D N o t e VM I D(pulse) f IN TA T CH(MAX) 0 PW < 5 ms, Duty < 10 % Condition MIN. 3.0 10.8 0.6 TYP. 3.3 12 MAX. 3.6 13.2 0.6 120 75 125 Unit V V A kHz °C °C
Note
The low-voltage malfunction prevention circuit (UVLO) operates when VDD is 2.1 V TYP.
CHARACTERISTICS TA = 25 °C and the other parameters are within their recommended operating ranges as described above
unless otherwise specified. The parameters other than changes in delay time are when the current is ON.
Parameter VM pin current (OFF state) VDD pin current High level input current Low level input current High level input voltage Low level input voltage H-bridge ON resistance (ch1, 3, 5, 6) H-bridge ON resistance (ch2, 4) H-bridge switching current without load (ch1, 3, 5, 6)Note H-bridge switching current without load (ch2, 4)Note
Symbol IM IDD I IH IIL VI H VI L RONa VM = 13.2 V VDD = 3.6 V VIN = VDD
Condition
MIN.
TYP.
MAX. 50 200 0.15
Unit
µA µA
mA
VIN = 0, IN and SEL pins VDD = 3.3 V, VM = 12 V IN and SEL pins
2.0 0 . 7 V DD 0.3 2.5 VDD 0 . 3 V DD 3.5
µA
V V mA
VDD = 3.3 V, VM = 12 V RONb upper + lower 1.5 2.0
Isa(AVE) VDD = 3.3 V, VM = 12 V Isb(AVE) 100 kHz switching
3.0
4.5
mA
Note
Average value of the current consumed internally by an H-bridge circuit when the circuit is switched without load.
2
Data Sheet S13908EJ1V0DS00
µPD16857
CHARACTERISTICS TA = 25 °C and the other parameters are within their recommended operating ranges as described above
unless otherwise specified. The parameters other than changes in delay time are when the current is ON.
Parameter Symbol (ch1, 3, 5 Rise time Rising delay time Change in rising delay time Fall time Falling delay time Change in falling delay time t TLHa t PLHa VDD = 3.3 V VM = 12 V RL(load) = 20 100 kHz switching Condition 1A, 1B, 3A, 3B, 5A, 5B output) 200 350 110 200 350 130 (ch1, 3, 5 Rising delay time differential Falling delay time differential t PLHa(A-B) t PHLa(A-B) 1A-1B, 3A-3B, 5A-5B) 50 50 ns ns ns ns ns ns ns ns MIN. TYP. MAX. Unit
tPLHa
t THLa t PHLa
tPHLa
VDD = 3.3 V, VM = 12 V RL = 20 , 100 kHz SW (ch2, 4 2A, 2B, 4A, 4B output)
Rise time Rising delay time Change in rising delay time Fall time Falling delay time Change in falling delay time
t TLHb t PLHb VDD = 3.3 V VM = 12 V RL(load) = 10 100 kHz switching
200 350 110 200 350 130 (ch2, 4 2A-2B, 4A-4B) 50 50
ns ns ns ns ns ns
tPLHb
t THLb t PHLb
tPHLb
Rising delay time differential Falling delay time differential
t PLHb(A-B) t PHLb(A-B)
VDD = 3.3 V, VM = 12 V RL = 10 , 100 kHz SW (ch6 6A, 6A output) 100
ns ns
Rise time Rising delay time Fall time Falling delay time
t TLHC tP L H C t THLC tP H L C
VDD = 3.3 V VM = 12 V RL(load) = 20 100 kHz switching
ns 1.0
µs
ns
100 1.0
µs
Data Sheet S13908EJ1V0DS00
3
|
|
