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Details, datasheet, quote on part number:UPD16879
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Datasheet text preview:
DATA SHEET
MOS INTEGRATED CIRCUIT
µPD16879
MONOLITHIC QUAD H BRIDGE DRIVER CIRCUIT
The µPD16879 is a monolithic quad H bridge driver IC that employs a CMOS control circuit and a MOSFET output circuit. Because it uses MOSFETs in its output stage, this driver IC consumes less power than conventional driver ICs that use bipolar transistors. Because the µPD16879 controls a motor by inputting serial data, its package has been shrunk and the number of pins reduced. As a result, the performance of the application set can be improved and the size of the set has been reduced. This IC employs a current-controlled 64-step micro step driving method that drives stepper motor with low vibration. The µPD16879 is a housed in a 38-pin shrink SOP to contribute to the miniaturization of application set. This IC can simultaneously drive two stepper motors and is ideal for the mechanisms of camcorders.
FEATURES
· Four H bridge circuits employing power MOS FETs · Current-controlled 64-step micro step driving · Motor control by serial data (8 bits × 13 bytes) PWM-frequency, output current and number of output pulse can be setting by serial data. · 3-V power supply. Minimum operating voltage: 2.7 V · Low consumption current. VDD pin current (operating mode) · Power save circuit bult in. VDD pin current (power save mode) : 100 µA (MAX.) VDD pin current (power save mode) : 300 µA (MAX.) · 38-pin shrink SOP (7.62 mm (300)) fCLK: OFF state fCLK: 4.5 MHz input : 3 mA (MAX.)
ORDERING INFORMATION
Part Number Pac k age 38-pin plastic shrink SOP (7.62 mm (300))
µPD16879GS-BGG
The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability and additional information.
Document No. S14188EJ1V0DS00 (1st edition) Date Published July 2000 N CP(K) Printed in Japan
©
2000
µPD16879
ABSOLUTE MAXIMUM RATINGS (TA = +25°C)
When mounted on a glass epoxy board (100 mm × 100 mm × 1 mm, 15% copper foil)
Parameter Supply voltage Symbol VDD VM Input voltage Reference voltage H bridge drive current VIN VREF IM(DC) IM(pulse) Power consumption Peak junction temperature Storage temperature PT TCH(MAX) Tstg External input DC PW < 10 ms, Duty < 5 % Conditions Control part Output part Rating 0.5 to +6.0 0.5 to +11.2 0.5 to VDD + 0.5 0.5 ±0.15 ±0.3 1.0 150 55 +150 Unit V V V V A/c h A/c h W °C °C
RECOMMENDED OPERATING RANGE (TA = +25°C)
When mounted on a glass epoxy board (100 mm × 100 mm × 1 mm, 15% copper foil)
Parameter Supply voltage Symbol VDD VM Input voltage Reference voltage EXP pin input voltage EXP pin input current H bridge drive current VIN VREF VEXPIN IEXPIN IM(DC) IM(pulse) Clock frequency (OSCIN) Clock frequency amplitude Serial clock frequency Video sync signal width LATCH signal wait time SCLK wait time SDATA setup time SDATA hold time Reset signal pulse width Operating temperautre Peak junction temperature fCLK VfCLK fSCLK PW(VD) t(VD-LATCH) t(SCLK-LATCH) tsetup thold tRST TA TCH(MAX) fCLK = 4.5 MHz Refer to Fig. 1 250 400 400 80 80 100 -10 85 125 DC PW < 10 ms, Duty < 5% COSC = 68 pF, VREF = 250 mV -0.1 -0.2 3.9 0.7 × VDD 4.5 External input Control part Output part Conditions MIN. 2.7 4.0 0 225 250 TYP. MA X . 5.5 11 VDD 275 VDD 100 +0.1 +0.2 6.0 VDD 5.0 Unit V V V mV V
µA
A/c h A/c h MHz V MHz ns ns ns ns ns
µs
°C °C
2
Data Sheet S14188EJ1V0DS00
µPD16879
ELECTRICAL CHARACTERISTICS
(Unless otherwise specified, TA = 25°C, VDD = 3 V, VM = 5.4 V, fCLK = 4.5 MHz, COSC = 68 pF, CFIL = 1000 pF, ° VREF = 250 mV, EVR = 100 mV (10000))
Parameter Off state VM pin current Operating state VDD pin current VDD pin current Power save state VDD pin current Symbol IMO(RESET) IDD IDD(RESET) IDD(PS)1 IDD(PS)2 High level input voltage Low level input voltage Input hysteresis vosltage Monitor output voltage 1 (EXTOUT , ) VI H VI L VH VOM(H) VOM(H) VOM(L) VOM(L) Monitor output voltage 2 (EXP 0,1 open drain) High level input current Low level input current Reset pin high level input current Reset pin low level input current H bridge ON resistance Chopping frequency
Note 1
Conditions No load, Reset period Output open Reset period tCLK = off fCLK = 4.5 MHZ LATCH, SCLK, SDATA, VD, VD RESET, OSCIN, VREFsel
MIN.
TYP.
MA X . 1.0 3.0 100 100 300
Unit
µA
mA
µA µA µA
V
0.7 × VDD 0.3 × VDD 0.3
V V V
4th byte
0.9 × VDD -0.3 0.9 × VDD 0.1 × VDD 1.0 -1.0 1.0 -1.0 6.0 Refer to table 1 (TYP.) 225 250 275 250 0.1 × VDD
V
VOEXP(H) VOEXP(L) II H IIL IIH(RST) IIL(RST) RON fOSC VREF
Pull up (VDD) IOEXP = 100 µA VIN = VDD VIN = 0 VRST = VDD VRST = 0 IM = 100 mA, upper + lower
V V
µA µA µA µA
kHz mV ns mA
Internal reference voltage VD delay time
Note 2
tVD
IM L = 15 mH/R = 70 ( 1 kHz) RS = 6.8 , fOSC = 72.58 kHz EVR = 220 mV (11100) EVR = 200 mV (11010) VREF = 250 mV external input Minimum step IM = 100 mA 370 53
Sin wave peak output current Note 3 (reference value)
FIL pin voltage
Note 4
VEVR
Note 4
400
430
mV
FIL pin step voltage
VEVRSTEP tONH tOFFH
20 2.0 2.0
mV
H bridge turn on time
Note 5
µs µs
H bridge turn off time
Note 5
Notes 1. When data are less than 7 (000111), PWM chopping doesn't do it, and output pulse doesn't occur. When data are beyong 49, PWM chopping frequency becomes a 225 kHz fixation. 2. By OSCIN and VD sync circuit 3. FB pin is monitored. 4. FIL pin is monitored. A voltage about twice that of the EVR value is output to the FIL pin. 5. 10% to 90% of the pulse peak value without filter capacitor (CFIL)
Data Sheet S14188EJ1V0DS00
3
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