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Details, datasheet, quote on part number:UPD17010GF
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Datasheet text preview:
DATA SHEET
MOS INTEGRATED CIRCUIT
µ PD17010
4-BIT SINGLE-CHIP MICROCONTROLLER WITH HARDWARE DEDICATED TO DIGITAL TUNING SYSTEM
T h e µPD17010 is a 4-bit single-chip CMOS microcontroller containing hardware for digital tuning systems. T h e CPU uses a 17K architecture and can directly manipulate the data memory and control various operations a n d peripheral hardware with a single instruction. All instructions are 16-bit 1-word instructions. A s the peripheral hardware, a prescaler for digital tuning that operates at up to 150 MHz, PLL frequency s y n t h e s i z e r , and frequency counter, as well as many I/O ports, LCD controller/driver, 12-bit timer, A/D converter, D / A converter (PWM output), clock generator port are provided. T h e r e f o r e , a high-performance digital tuning system with sophisticated functions can be configured with a s i n g l e chip. The µPD17P010 is available as a one-time PROM model of the µPD17010. This one-time PROM m o d e l can be used for evaluation of the program of the µPD17010 and small-scale production of the application system.
FEATURES · 1 7 K architecture: General-purpose register
system
· A variety of peripheral hardware
G e n e r a l - p u r p o s e I/O ports, LCD controller/driver, s e r i a l interface, 12-bit timer, A/D converter, D/A c o n v e r t e r (PWM output), clock generator port, f r e q u e n c y counter
· P r o g r a m memory (ROM)
1 6 K bytes (7932 × 16 bits)
· G e n e r a l - p u r p o s e data memory (RAM)
4 3 2 × 4 bits
· M a n y interrupts
External: 1 Internal: 4 E x t e r n a l / i n t e r n a l (multiplexed): 1
· I n s t r u c t i o n execution time
4 . 4 4 µs (with 4.5-MHz crystal resonator)
· D e c i m a l operation · T a b l e reference · H a r d w a r e for PLL frequency synthesizer
D u a l modulus prescaler (150 MHz MAX.), p r o g r a m m a b l e divider, phase comparator, c h a r g e pump
· P o w e r - O N reset, reset by CE pin, and power failure d e t e c t i o n circuit · L o w power-dissipation CMOS · S u p p l y voltage: 5 V±10 %
The information in this document is subject to change without notice. Document No. U10340EJ2V0DS00 (2nd edition) (Previous No. ID-2878) Date Published October 1995 P Printed in Japan
©
1991
µPD17010
ORDERING INFORMATION
Part Number Package 80-pin plastic QFP (14 × 20 mm) 80-pin plastic QFP (14 × 20 mm)
µP D 1 7 0 1 0 G F -××× - 3 B 9 µ P D 1 7 0 1 0 G F - E × ×- 3 B 9 Note
Note
Model supporting I2C bus. To use the I2C bus (including when the function is implemented by program without using the peripheral hardware), consult NEC when ordering mask.
Remark ××× indicates a ROM code.
FUNCTIONAL OUTLINE
Item Program memory (ROM) · 16K bytes (7932 × 16 bits) All internal ROM areas can be referenced through table General-purpose data memory (RAM) · 432 × 4 bits Data buffer : 4 × 4 bits, general register : 16 × 4 bits System register Register file General-purpose port register (including LCD dot data register) Instruction execution time Stack level General-purpose ports · 4.44 µs (with 4.5-MHz crystal resonator) · 9 levels (stack can be manipulated) · I/O ports : 16 · Input ports : 8 · Output ports : 9 (+30: LCD segment pin) Clock generator port (CGP) ·1 VDP (Variable Duty Pulse) and SG (Signal Generator) functions LCD controller/driver · 30 segments, 2 commons 1/2 duty, 1/2 bias, frame frequency: 250 MHz, drive voltage: VDD Segment pins multiplexed with key source: 16 All 30 pins can be used as output port pins (4, 4, 6, and 16 pins can be independently set) Serial interface · 2 systems (3 channels) Serial interface 0 : 2-line (I2C bus, serial I/O) 3-line (serial I/O) Serial interface 1 : 3-line (serial I/O) D/A converter A/D converter · 8 bits × 3 (PWM output, output voltage: 16 V MAX.) · 6 bits × 6 (successive approximation via software) · 12 × 4 bits · 41 × 4 bits (control register) · 24 × 4 bits Function
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µPD17010
Item Interrupt · 6 (maskable interrupts) External : 1 (INT0 pin)
Function
Internal : 4 (12-bit timer, basic timer 1, serial interface 0, frequency counter) External/internal (multiplexed) : 1 (INT1 pin or overflow of timer/counter) Timer · 3 channels 12-bit timer (1, 50 µs) Basic timer 0 carry (1, 5, 100, 250 ms) Basic timer 1 interrupt (1, 5, 100, 250 ms) Reset · Power-ON reset (on power up) · Reset by CE pin (CE pin low level high level) · Power failure detection function PLL frequency synthesizer Division method · 2 types Direct division (VCOL pin: 30 MHz MAX.) Pulse swallow (VCOL pin: 40 MHz MAX.) (VCOH pin: 150 MHz MAX.) Reference frequency · 12 types selectable by program 1, 1.25, 2.5, 3, 5, 6.25, 9, 10, 12.5, 25, 50, 100 kHz Charge pump Phase comparator · Two independent error out outputs · Unlock detection programmable Delay time of unlock F/F selectable Frequency counter · Frequency measurement P1D3/FMIFC pin : 5 to 15 MHz P1D2/AMIFC pin : 0.1 to 1 MHz · External gate width measurement P1A0/FCG pin Supply voltage Package 5 V ± 10 % 80-pin plastic QFP (14 × 20 mm)
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