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Details, datasheet, quote on part number:UPD488448FF-C60-53-DQ2
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Datasheet text preview:
DATA SHEET
µPD488448 for Rev. P
128 M-bit Direct RambusTM DRAM
MOS INTEGRATED CIRCUIT
Description
The Direct Rambus DRAM (Direct RDRAMTM) is a general purpose high-performance memory device suitable for use in a broad range of applications including computer memory, graphics, video, and any other application where high bandwidth and low latency are required. The µPD488448 is 128M-bit Direct Rambus DRAM (RDRAM®), organized as 8M words by 16 bits. The use of Rambus Signaling Level (RSL) technology permits 600 MHz to 800 MHz transfer rates while using conventional system and board design technologies. Direct RDRAM devices are capable of sustained data transfers at 1.25 ns per two bytes (10 ns per sixteen bytes). The architecture of the Direct RDRAMs allows the highest sustained bandwidth for multiple, simultaneous randomly addressed memory transactions. The separate control and data buses with independent row and column control yield over 95% bus efficiency. The Direct RDRAM's thirty-two banks support up to four simultaneous transactions. System oriented features for mobile, graphics and large memory systems include power management, byte masking. The µPD488448 is offered in a CSP horizontal package suitable for desktop as well as low-profile add-in card and mobile applications. Direct RDRAMs operate from a 2.5 volt supply.
Features
· Highest sustained bandwidth per DRAM device - 1.6 GB/s sustained data transfer rate - Separate control and data buses for maximized efficiency - Separate row and column control buses for easy scheduling and highest performance - 32 banks: four transactions can take place simultaneously at full bandwidth data rates · Low latency features - Write buffer to reduce read latency - 3 precharge mechanisms for controller flexibility - Interleaved transactions · Advanced power management: - Multiple low power states allows flexibility in power consumption versus time to transition to active state - Power-down self-refresh · Overdrive current mode · Organization: 1 Kbyte pages and 32 banks, x 16 · Uses Rambus Signaling Level (RSL) for up to 800 MHz operation · Package : 62-pin TAPE FBGA (µBGA®) and 62-pin PLASTIC FBGA (D BGATM (Die Dimension Ball Grid Array) )
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Not all devices/types available in every country. Please check with local NEC representative for availability and additional information.
Document No. M14837EJ3V0DS00 (3rd edition) Date Published August 2000 NS CP (K) Printed in Japan
The mark · shows major revised points.
©
2000
µPD488448 for Rev. P
Ordering Information
Part number Organization Note Clock frequency (MAX.) RAS access time (ns) 53 45 45 53 45 45 53 45 45 53 45 45 62-pin PLASTIC FBGA (D2BGA) (Mirrored type) 62-pin PLASTIC FBGA (D2BGA) (Normal type) 62-pin TAPE FBGA (µBGA) (Mirrored type) 62-pin TAPE FBGA (µBGA) (Normal type) Package
µPD488448FF-C60-53-DQ1 µPD488448FF-C71-45-DQ1 µPD488448FF-C80-45-DQ1 µPD488448FF-C60-53-DQ2 µPD488448FF-C71-45-DQ2 µPD488448FF-C80-45-DQ2 µPD488448FB-C60-53-DQ1 µPD488448FB-C71-45-DQ1 µPD488448FB-C80-45-DQ1 µPD488448FB-C60-53-DQ2 µPD488448FB-C71-45-DQ2 µPD488448FB-C80-45-DQ2
256K x 16 x 32s
600 MHz 711 MHz 800 MHz 600 MHz 711 MHz 800 MHz 600 MHz 711 MHz 800 MHz 600 MHz 711 MHz 800 MHz
Note The "32s" designation indicates that this RDRAM core is composed of 32 banks which use a "split" bank architecture.
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Data Sheet M14837EJ3V0DS00
µPD488448 for Rev. P
Pin Configurations
62-pin TAPE FBGA (µBGA) (Normal type) µ 62-pin PLASTIC FBGA (D2BGA) (Normal type)
Top View
Ball View
12 11 10 9 8 7 6 5 4 3 2 1 ABCDEFGHJ JHGFEDCBA
12 11 10 9 8 7 6 5 4 3 2 1
12 11 10 9 8 7 6 5 4 3 2 1
GND
VDD
VDD
GND
GND
VDD
VDD
GND
12 11
DQA7 DQA4 CFM CFMN RQ5 GND VDD GND GNDa VDD RQ6
RQ3 DQB0 DQB4 DQB7 GND VDD VDD GND
DQB7 DQB4 DQB0 RQ3 GND VDD VDD GND
RQ5 CFMN CFM DQA4 DQA7 VDD RQ6 GNDa GND VDD GND
10 9 8 7 6
CMD DQA5 DQA2 VDDa
RQ2 DQB1 DQB5 SIO1
SIO1 DQB5 DQB1 RQ2
VDDa DQA2 DQA5 CMD
SCK DQA6 DQA1 VREF VCMOS GND NC
No t e
RQ7 GND
R Q1 DQB2 DQB6 SIO0 VDD RQ4 GND GND VCMOS
No t e
SIO0 DQB6 DQB2 RQ1 VCMOS GND NC
No t e
R Q7 GND
VREF DQA1 DQA6 SCK GND VDD GND VCMOS
No t e
5 4 3 2
VDD
GND
GND
VDD R Q4
DQA3 DQA0 CTMN CTM
RQ0 DQB3 NC
DQB3 RQ0
CTM CTMN DQA0 DQA3 NC
GND
VDD
VDD
GND
GND
VDD
VDD
GND
1
A
B
C
D
E
F
G
H
J
J
H
G
F
E
D
C
B
A
Note Some signals can be applied because this pin is not connected to the inside of the chip.
Data Sheet M14837EJ3V0DS00
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