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Details, datasheet, quote on part number:UPD4990AC
 
 
Part:UPD4990AC
Category:Logic
Description:Serial I/o Calendar & Clock CMOS Lsi
Company:NEC Electronics Inc.
Datasheet:Download UPD4990AC datasheet   File size : 133 kB
Request For quote:  Find where to buy UPD4990AC
 



Datasheet text preview:
DATA SHEET
MOS INTEGRATED CIRCUIT
µPD4990A
SERIAL I/O CALENDAR & CLOCK CMOS LSI
The µPD4990A is a CMOS LSI developed to input/output calendar & clock data serially to/from the micro computer. The crystal frequency is 32.768 kHz and the data items included are time, minute, second, year, month, day, and week.
FEATURES
· · · · ·
Built-in counters for time (hour, minute, and second) and date (year, month, day, and week) Leap years are adjusted automatically. Data is represented in BCD notation (except months in hexadecimal notation) and input/output serially. Commands can be set by inputting serial data. Selective timing pulses (TPs) are 64 Hz, 256 Hz, 2 048 Hz, and 4 096 Hz and selective output intervals are 1, 10, 30, and 60 seconds.
ORDERING INFORMATION
PART No. PACKAGE 14-pin plastic DIP (300 mil) 16-pin plastic SOP (300 mil)
µP D 4 9 9 0 A C µP D 4 9 9 0 A G
CONNECTION DIAGRAM (Top View)
C2 C1 C0 STB CS DATA IN GND (VSS)
1 2 3 4 5 6 7
14 13 12 11 10 9 8
VDD (+) XTAL XTAL OUT ENBL TP DATA OUT CLK
C2 C1 C0 NC STB CS DATA IN GND (VSS)
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
VDD (+) XTAL XTAL NC OUT ENBL TP DATA OUT CLK
µ PD4990AC
µ PD4990AG
NC: NO CONNECTION
Document No. IC-1755 (1st edition) Date Published March 1997 P Printed in Japan
©
1989
µPD4990A
ABSOLUTE MAXIMUM RATINGS
Supply Voltage Input Voltage Operating Temperature Range Storage Temperature Range Output Terminal Voltage VDD - VSS VIN Topt T stg VOUT -0.5 to 7.0 VSS -0.3 to VDD +0.3 - 40 to +85 -65 to +125 -0.5 to 7.0 V V °C °C V
ELECTRICAL CHARACTERISTICS (f = 32.768 kHz, CG = CD = 20 pF, CI = 20 k, Ta = 25 °C)
CHARACTERISTIC Operating Voltage Current Consumption SYMBOL VDD - VSS I DD 100 Low Level Output Voltage CLK Input Frequency Input Leakage Current High Level Input Voltage Low Level Input Voltage V OL f CLK I IN V IH V IL 0.7 VDD V SS DC 0.4* 500 ±1 VDD 0.3 VDD MIN. 2.00 8 TYP. MAX. 5.50 20 UNIT V TEST CONDITIONS
µA µA
V kHz
VDD - VSS = 3.60 V VDD - VSS = 5.50 V VDD - VSS = 2.0 to 5.5 V IOL = 500 µA VDD - VSS = 2.0 V, Duty 50 % VDD - VSS = 5.50 V
µA
V V
* TP and DATA OUT are N-channel open drain output.
A.C. ELECTRICAL CHARACTERISTICS (f = 32.768 kHz, VDD - VSS = 2.0 V, Ta = 25 °C)
CHARACTERISTIC C0 to 2, CS - STB Set-up Time STB Pulse Width C0 to 2, CS - STB Hold Time STB LATCH Delay Time CLK-DATA OUT Delay time DATA IN Set-up Time DATA IN Hold Time SYMBOL tSU tSTB t HLD td1 td(c-o) t DSU t DHLD 1 1 MIN. 1 1 1 1** 1 TYP. MAX. UNIT TEST CONDITIONS
µs µs µs µs µs µs µs
except Time Read mode RL = 33 k, CL = 15 pF
** Note: When a function mode is Time Read mode (other than Test mode), STB LATCH delay time is 20 µs MAX. ( t d2 ) .
2
BLOCK DIAGRAM
OE N-ch OPEN DRAIN DATA OUT MPX
CLK DATA IN
CLK COMMAND Register
48 Bit Shift Register
CLK RH CS C3' C2' C1' C0' 1 Hz
YEAR PS
MON -TH D/W
DAY HOUR
MIN
SEC
Time counter 15 Stage Binary Divider XTAL XTAL OSC Select signal generator circuit 1/215
64 Hz STOP 1 Hz
C3' C2' C1' C0' C2 C1 C0
DATA SELECTOR
DECODER
1/26 TEST
SEC RESET TP MPX
MPX : Multiplexer CS PS : Preset D/W : Day of the Week CS STB TP RH : Chip Select : Timing Pulse : Register Hold
µP D 4 9 9 0 A
3