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Details, datasheet, quote on part number:UPD70325GJ-8-5BG
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Datasheet text preview:
DATA SHEET
MOS INTEGRATED CIRCUIT
µPD70325
V25+TM 16/8-BIT SINGLE-CHIP MICROCONTROLLER
The µPD70325 (V25+) is a single-chip microcontroller on which 16-bit CPU, RAM, serial interface, timer, DMA controller, interrupt controller, etc. are all integrated. The µPD70325 is software compatible with the 16/8-bit singlechip microcontroller µPD70320 (V25TM). The V25+ greatly improves the DMA responsivity and transfer rate compared to the V25.
FEATURES
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Software compatible with V25 Software compatible with µPD70108/70116 (in native mode) (some instructions added) Internal 16-bit architecture and external 8-bit data bus 3-stage pipeline method Minimum instruction cycle : 250 ns/8 MHz (external 16 MHz) : 200 ns/10 MHz (external 20 MHz) Memory space 1 Mbyte On-chip RAM : 256 words × 8 bits Register bank (memory mapped method) : 8 banks Input port (port T) with comparator : 8 bits I/O lines (input port : 4 bits, input/output ports : 20 bits) Serial interface : 2 channels · Internal dedicated baud rate generator · Asynchronous mode and I/O interface mode
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Interrupt controller · Programmable priority (8 levels) · 3 types of interrupt response method Vectored interrupt function, register bank switching function, macro service function
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DRAM and pseudo SRAM refreshing function DMA controller : 2 channels · 4 types of DMA transfer mode · Transfer rate Maximum 4 Mbytes/second (when stop control is not executed by DMARQ pin in demand release mode) Maximum 2 Mbytes/second (when stop control is executed by DMARQ pin in demand release mode, or burst mode) · Address pointer (linear) : 20 bits · Terminal counter : 16 bits
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16-bit timer : 2 channels Time base counter (20 bits) : 1 channel On-chip clock generator Programmable wait function Standby function (STOP, HALT)
The information in this document is subject to change without notice.
Document No. U12850EJ7V0DS00 (7th edition) Date Published November 1997 N Printed in Japan
The mark
shows major revised points.
©
1996 1995
µPD70325
ORDERING INFORMATION
Part Number Package 94-pin plastic QFP (20 × 20 mm) 94-pin plastic QFP (20 × 20 mm) 84-pin plastic QFJ (1150 × 1150 mil) 84-pin plastic QFJ (1150 × 1150 mil) External Clock (MHz) 16 20 16 20
µP D 7 0 3 2 5 G J - 8 - 5 B G µP D 7 0 3 2 5 G J - 1 0 - 5 B G µP D 7 0 3 2 5 L - 8 µP D 7 0 3 2 5 L - 1 0
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µPD70325
Comparison between V25 and V25+
V25 V35TM V25+ V35+ TM
µP D 7 0 3 2 0
Transfer processing method Maximum transfer rate (8-MHz operation) Sampling timing of DMA request DMA service channel
µP D 7 0 3 3 0
µP D 7 0 3 2 5
µP D 7 0 3 3 5
Depends on microprogram 0.6 Mbytes/second 0.8 Mbytes/second
Depends on dedicated hardware 4 Mbytes/second 5.3 Mbytes/second
Between instruction execution cycles In on-chip RAM area
Between bus cycles In special function register Linear method 1 DMA transfer/1 bus cycle Not accepted
Specification method of transfer address Segment method Execution format in single-step mode 1 DMA transfer/1 instruction execution DMA Interrupt request during DMA transfer Accepts only NMI function (demand release mode) Number of necessary waits when stop is controlled by DMARQ (demand release mode) Transfer processing units TC (terminal counter) setting value Not necessary
2 waits
Byte/word
Byte/word
Byte
Byte/word
Number of times of DMA transfer
(Number of times of DMA transfer) 1 TC = FFFFH Expanded by wait insertion Available (SCK0 pin)
Generation timing of terminal counter TC = 0 TC output low-level width Transmit clock output in asynchronous mode (channel 0) Serial error register Serial interface Receive buffer full flag Transmit buffer empty flag All sent flag Interrupt Interrupt source register function External data bus Maximum operating frequency Fixed Not available
Yes No No No No 8 bits 8 MHz 16 bits
Serial status register In serial status register In serial status register In serial status register Yes 8 bits 10 MHz 16 bits
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