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Details, datasheet, quote on part number:UPD705101
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Datasheet text preview:
DATA SHEET
MOS INTEGRATED CIRCUIT
µPD705101
V831TM 32-BIT MICROPROCESSOR
DESCRIPTION
The µPD70501 (V831) is a 32-bit RISC microprocessor for embedded control applications, with a high-performance 32-bit V830TM processor core and many peripheral functions such as a DRAM/ROM controller, 4-channel DMA controller, real-time pulse unit, serial interface, and interrupt controller. In addition to high interrupt response speed and optimized pipeline structure, the V831 offers sum-of-products operation instructions, concatenated shift instructions, and high-speed branch instructions to realize multimedia functions, and therefore, can provide high performance in multimedia systems such as internet/intra-net systems, car navigation systems, high-performance televisions, and color FAXes. Detailed explanations of the functions, etc. are given in the following user's manuals. Be sure to read the manuals before designing your systems. V831 User's Manual -Handware V830 FamilyTM : U12273E User's Manual -Architecture : U12496E · · : 4 KB : 4 KB : 4 KB : 4 KB : 1 cycle : 32 bits × 32 : 4 GB each · · · · · DMA controller : 4 channel
FEATURES
· CPU function · V830-compatible instructions · Instruction cache · Instruction RAM · Data cache · Data RAM · Minimum number of instruction execution cycles · Number of general purpose registers · Memory space and I/O space · Interrupt/exception function · Non-maskable : External input : 1 · Maskable : External input : 8 (of which 4 are multiplexed with internal sources) Internal source: 11 types · · · Bus control function Wait control function Memory access control function
Serial interface function · Asynchronous serial interface (UART): 1 channel · Clocked serial interface (CSI) Timer/counter function · 16-bit timer/event counter : 1 channel · 16-bit interval timer Port function Standby function Debug function · Debug-dedicated synchronous serial interface · Trace-dedicated interface : 1 channel : 1 channel : 1 channel : 3 I/O ports : HALT and STOP modes : 1 channel · Dedicated baud rate generator (BRG) : 1 channel
Clock generation function : PLL clock synthesizer
The information in this document is subject to change without notice. Document No. U12979EJ1V0DS00 (1st edition) Date Published January 1998 N Printed in Japan
©
1998
µPD705101
ORDERING INFORMATION
Part Number Package 160-pin plastic LQFP (fine pitch) (24 × 24 mm)
µP D 7 0 5 1 0 1 G M - 1 0 0 - 8 E D
PIN CONFIGURATION (TOP VIEW)
· 160-pin plastic LQFP (fine pitch) (24 × 24 mm)
µP D 7 0 5 1 0 1 G M - 1 0 0 - 8 E D
GND D2 D3 D4 D5 D6 D7 D8 VDD GND D9 D10 D11 VDD GND D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 VDD GND D22 D23 D24 VDD GND D25 D26 D27 D28 D29 D30 D31 VDD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121
V DD D1 D0 LLCAS LUCAS ULCAS UUCAS RAS OE WE A1 GND V DD GND V DD A2 A3 A4 A5 A6 A7 A8 A9 GND V DD A10 A11 GND V DD A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 GND
120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
VDD CLKOUT TRCDATA0 TRCDATA1 TRCDATA2 TRCDATA3 DDI DCK DMS DDO A22 A23 GND VDD IOWR IORD BCYST READY HLDRQ HLDAK CS1 CS2 GND VDD CS3 CS4 CS5 GND VDD CS6 CS7 INTP10/TO10 INTP12/TO11 INTP11 INTP13 TI TCLR INTP00 INTP01 GND
2
GND LLMWR LUMWR ULMWR UUMWR MRD TXD RXD GND VDD PORT2/SI PORT1/SO PORT0/SCLK VDD_PLL X1 X2 GND_PLL GND VDD GND VDD RESET DRST NMI BT16B GND VDD GND DMAAK0 DMAAK1 DMAAK2 DMAAK3 DMARQ0 DMARQ1 DMARQ2 DMARQ3 TC/REFRQ INTP03 INTP02 VDD
41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
µPD705101
PIN NAMES
A1-A23 BCYST BT16B CLKOUT CS1-CS7 D0-D31 DCK DDI DDO
: Address Bus : Bus Cycle Start : Boot Bus Size 16 bit : Clock Out : Chip Select : Data Bus : Debug Clock : Debug Data Input : Debug Data Output
NMI OE PORT0-PORT2 RAS READY REFRQ RESET RXD SCLK SI SO TC TCLR TI TO10, TO11
: Non-Maskable Interrupt Request : Output Enable : Port : Row Address Strobe : Ready : Refresh Request : Reset : Receive Data : Serial Clock : Serial Input : Serial Output : Terminal Count : Timer Clear : Timer Input : Timer Output : Trace Data
DMAAK0-DMAAK3 : DMA Acknowledge DMARQ0-DMARQ3: DMA Request DMS DRST GND GND_PLL HLDAK HLDRQ : Debug Mode Select : Debug Reset : Ground : PLL Ground : Hold Acknowledge : Hold Request
TRCDATA0-TRCDATA3 TXD ULCAS ULMWR UUCAS UUMWR V DD V D D_ P L L WE X1, X2 : Transmit Data : Upper Lower Column Address Strobe : Upper Lower Memory Write : Upper Upper Column Address Strobe : Upper Upper Memory Write : Power Supply : PLL Power Supply : Write Enable : Crystal Oscillator
INTP00-INTP03, INTP10-INTP13 : Interrupt Request From Peripheral IORD IOWR LLCAS LLMWR LUCAS LUMWR MRD : I/O Read : I/O Write : Lower Lower Column Address Strobe : Lower Lower Memory Write : Lower Upper Column Address Strobe : Lower Upper Memory Write : Memory Read
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