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Details, datasheet, quote on part number:UPD705102
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DATA SHEET
MOS INTEGRATED CIRCUIT
µPD705102
V 8 3 2 TM 32-BIT MICROPROCESSOR
DESCRIPTION
The µPD705102 (V832) is a 32-bit RISC microprocessor for embedded control applications, with a highperformance 32-bit V830TM processor core and many peripheral functions such as a SDRAM/ROM controller, 4channel DMA controller, real-time pulse unit, serial interface, interrupt controller, and power management. In addition to high interrupt response speed and optimized pipeline structure, the V832 offers sum-of-products operation instructions, concatenated shift instructions, and high-speed branch instructions to realize multimedia functions, and therefore can provide high performance in multimedia systems such as Internet/intra-net systems, car navigation systems, digital still cameras, and color faxes. Detailed function descriptions are provided in the following user's manuals. Be sure to read them before designing. V832 User's Manual -- Hardware: U13577E V830 FamilyTM User's Manual -- Architecture: U12496E
FEATURES
· CPU function · V830-compatible instructions · Instruction cache: · Instruction RAM: · Data cache: · Data RAM: · Minimum number of instruction execution cycles: · Number of general purpose registers: 32 bits × 32 · Memory space and I/O space: 4 Gbytes each · Interrupt/exception processing function · Non-maskable: External input: 1 · Maskable: External input: 8 (of which 4 are multiplexed with internal sources) Internal source: 11 types · Bus control function · Wait control function · Memory access control function
The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. U13675EJ2V1DS00 (2nd edition) Date Published July 1999 N CP(K) Printed in Japan
· DMA controller: 4 channels · Serial interface function 4 Kbytes 4 Kbytes 4 Kbytes 4 Kbytes 1 cycle · Asynchronous serial interface (UART): 1 channel · Clocked serial interface (CSI): · Timer/counter function · 16-bit timer/event counter: 1 channel · 16-bit interval timer: · Port function: 21 I/O ports · Clock generation function: PLL clock synthesizer (6× or 8× multiplication) · Standby function: HALT, STOP, and power management modes · Debug function · Debug-dedicated synchronous serial interface: · Trace-dedicated interface: 1 channel 1 channel 1 channel 1 channel · Dedicated baud rate generator (BRG): 1 channel
The mark
shows major revised points.
©
1999
µPD705102
ORDERING INFORMATION
Part Number Package 160-pin plastic LQFP (fine pitch) (24 × 24 mm) 160-pin plastic LQFP (fine pitch) (24 × 24 mm)
µP D 7 0 5 1 0 2 G M - 1 4 3 - 8 E D µP D 7 0 5 1 0 2 G M - 1 3 3 - 8 E D
PIN CONFIGURATION (TOP VIEW)
· 160-pin plastic LQFP (fine pitch) (24 × 24 mm)
µP D 7 0 5 1 0 2 G M - 1 4 3 - 8 E D µP D 7 0 5 1 0 2 G M - 1 3 3 - 8 E D
VDD_O D31 D30 D29 D28 D27 D26 D25 D24 GND_I VDD_I GND_O VDD_O D23 D22 D21 D20 D19 D18 D17 D16 GND_O VDD_O D15 D14 D13 D12 D11 D10 D9 D8 GND_O VDD_O D7 D6 D5 D4 D3 D2 GND_I
GND_O CS1 CS0 WE RAS UUDQM ULDQM LUDQM LLDQM VDD_O GND_O SDCLKOUT CKE CAS A1 A2 A3 A4 VDD_I GND_I VDD_O GND_O A5 A6 A7 A8 A9 A10 A11 VDD_O GND_O A12 A13 A14 A15 A16 A17 A18 A19 VDD_O
160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
VDD_I D1 D0 GND_O VDD_O MRD MWR LLBEN LUBEN ULBEN UUBEN IOWR IORD BCYST READY R/W HLDRQ HLDAK GND_O VDD_O CS2 CS3 CS4 CS5 CS6 CS7 TC/STOPAK PORTA1/DMAAK0 PORTA3/DMAAK1 PORTA5/DMAAK2 PORTA7/DMAAK3 PORTA0/DMARQ0 PORTA2/DMARQ1 PORTA4/DMARQ2 PORTA6/DMARQ3 PORTB7/INTP03 PORTB6/INTP02 PORTB4/INTP01 PORTB2/INTP00 GND_I
Caution
Directly connect the IC1 (Internally connected 1) pin to GND_O.
2
GND_O A20 A21 A22 A23 CLKOUT TRCDATA0 TRCDATA1 TRCDATA2 TRCDATA3 DDI DCK DMS DDO VDD_PLL X1 X2 GND_PLL VDD_I GND_I IC1 BT16B RESET NMI DRST CMODE PORT3/RXD PORT4/TXD PORT2/SI PORT1/SO PORT0/SCLK VDD_O GND_O INTP10/TO10 INTP12/TO11 PORTB5/INTP11 PORTB3/INTP13 PORTB0/TI PORTB1/TCLR VDD_I
41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
Data Sheet U13675EJ2V1DS00
µPD705102
PIN NAMES
A1 to A23: BCYST: BT16B: CAS: CKE: CLKOUT: CMODE: CS0 to CS7: D0 to D31: DCK: DDI: DDO: Address Bus Bus Cycle Start Boot Bus Size 16-bit Column Address Strobe Clock Enable Clock Out Clock Mode Chip Select Data Bus Debug Clock Debug Data Input Debug Data Output DMA Acknowledge DMARQ0 to DMARQ3: DMA Request DMS: DRST: GND_I: GND_O: GND_PLL: HLDAK: HLDRQ: IC1: Debug Mode Select Debug Reset Ground Ground PLL Ground Hold Acknowledge Hold Request Internally Connected Interrupt Request From Peripheral IORD: IOWR: LLBEN: LLDQM: LUBEN: LUDQM: MRD: MWR: I/O Read I/O Write Lower Lower Byte Enable Lower Lower DQ Mask enable Lower Upper Byte Enable Lower Upper DQ Mask enable Memory Read Memory Write NMI: PORT0 to PORT4, PORTA0 to PORTA7, PORTB0 to PORTB7: Port R/W: RAS: READY: RESET: RXD: SCLK: SDCLKOUT: SI: SO: STOPAK: TC: TCLR: TI: TO10, TO11: TXD: ULBEN: ULDQM: UUBEN: UUDQM: V DD _ I : V DD _ O : V DD _ P L L : WE: X1, X2: Bus Read or Write Status Row Address Strobe Ready Reset Receive Data Serial Clock SDRAM Clock Out Serial Input Serial Output Stop Acknowledge Terminal Count Timer Clear Timer Input Timer Output Transmit Data Upper Lower Byte Enable Upper Lower DQ Mask enable Upper Upper Byte Enable Upper Upper DQ Mask enable Power Supply (2.5 V) Power Supply (3.3 V) PLL Power Supply (2.5 V) Write Enable Crystal Oscillator Non-Maskable Interrupt Request
DMAAK0 to DMAAK3:
TRCDATA0 to TRCDATA3: Trace Data
INTP00 to INTP03, INTP10 to INTP13:
Data Sheet U13675EJ2V1DS00
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