|
|
Part: UPD72850AGK-9EU
Category:
Interface and Interconnect
-> IEEE 1394 (Firewire)
Description: IEEE1394 400Mbps PHY
Company: NEC Electronics Inc.
Datasheet: Download UPD72850AGK-9EU datasheet File size : 1637 kB
Request For quote: Find where to buy UPD72850AGK-9EU
Datasheet text preview:
DATA SHEET
MOS INTEGRATED CIRCUIT
µPD72850A
IEEE1394 400Mbps PHY
The µPD72850A is the 3-port physical layer LSI which complies with the P1394a draft 2.0 specifications. The µPD72850A works up to 400 Mbps. It is an upgrade of NEC's µPD72850.
FEATURES
· The Three-port Physical Layer LSI complies to IEEE P1394a draft 2.0 · Connection debounce · Arbitration enhancements · Arbitrated short bus reset · Ack-accelerated arbitration · Fly-by concatenation · Multiple-speed packet concatenation · Arbitration enhancements and cycle start (controlled by the Link layer) · Performance optimization via PHY pinging · Priority arbitration (controlled by the Link layer) · Data rate: 393.216 / 196.608 / 98.304 Mbps · Compliant with Suspend/Resume function as defined in P1394a draft 2.1 · 3.3 V single power supply · Electrical isolated Link interface · 24.576 MHz crystal clock generation, 393.216 MHz PLL multiplying frequency · System power management by signaling of node power class information · Cable power monitor (CPS) is equipped · Fully interoperable with IEEE1394 std 1394 Link (FireWireTM, i.LINKTM) · Cable bias and terminal voltage driver supply function (for 3-port each) · Separate digital power and analog GND · Enable/Disable port control switch when power supply is powered on · Support Suspend/Resume Off mode (Compliant with P1394a draft 1.3) · Number of supported port are selectable · 1port, 2port, 3port. This selection is only under Suspend/Resume Off mode · Compliant with MD8405E (FUJIFILM MICRODEVICES CO., LTD)
ORDERING INFORMATION
Part number Package 80-pin plastic TQFP (Fine pitch) (12 x 12 mm)
µPD72850AGK-9EU
The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability and additional information.
Document No. S14452EJ1V0DS00 (1st edition) Date Published October 1999 NS CP(K) Printed in Japan
1999
µPD72850A
BLOCK DIAGRAM
CMC PC0 PC1 PC2 PORTDIS PSEL SUS/RES LREQ LPS DIRECT SCLK LKON CTL0 CTL1 D0 D1 D2 D3 D4 D5 D6 D7
TpA0p TpA0n
Cable Port1
TpB0p TpB0n
Arbitration and Control State Machine Logic Cable Port2 Link Interface I/O Cable Port3
TpA1p TpA1n TpB1p TpB1n TpA2p TpA2n TpB2p TpB2n TpBias0 TpBias1 TpBias2 R0 R1 XI XO FIL0 FIL1
Receive Data Decoder and Retimer
Voltage and Current Generator Crystal Oscillator PLL System and Transmit Clock Generator
RESETB CPS Cable Power Status
Transmit Data Encoder
2
Data Sheet S14452EJ1V0DS00
µPD72850A
PIN CONFIGURATION (Top View)
· 80-pin plastic TQFP (Fine pitch) (12 x 12 mm)
PC1 PC0 CMC DGND LPS LREQ DVDD DGND SCLK DVDD DGND CTL0 CTL1 DVDD D0 D1 DGND D2 D3 DGND
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
DVDD PC2 LKON DIRECT IC(H) IC(H) DGND AVDD AGND SUS/RES AGND AGND AGND AVDD PSEL AGND PORTDIS AVDD AGND AGND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
TpA0p TpA0n TpB0p TpB0n TpA1p TpA1n TpB1p TpB1n TpA2p TpA2n TpB2p TpB2n TpBias0 TpBias1 TpBias2 AVDD AGND CPS RI1 RI0
D4 D5 DGND D6 D7 DVDD DVDD DVDD DGND RESETB AVDD AGND AGND FIL1 FIL0 AVDD XI XO AGND AVDD
Data Sheet S14452EJ1V0DS00
3
Others parts begin by up
UP-1 UP-2 UP-3 UP-4 UP-5 UP-6 UP-7 UP-8 UP-9 UP-10 UP-11 UP-12 UP-13 UP-14 UP-15 UP-16 UP-17 UP-18 UP-19 UP-20 UP-21 UP-22 UP-23 UP-24 UP-25 UP-26 UP-27 UP-28
|
|
|
