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Part: UPD72862
Category:
Interface and Interconnect
-> IEEE 1394 (Firewire)
Description: Ieee1394 Ohci Host Controller
Company: NEC Electronics Inc.
Datasheet: Download UPD72862 datasheet File size : 1637 kB
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Datasheet text preview:
DATA SHEET
MOS INTEGRATED CIRCUIT
µPD72862
IEEE1394 OHCI HOST CONTROLLER
The µPD72862 is IEEE1394 OHCI-Link controller. The µPD72862 complies with the P1394a draft 2.0 specifications and works up to 400 Mbps. It supports both of the Cardbus interface and the PCI bus interface.
FEATURES
· Compliant with Link Layer Services as defined in 1394 Open Host Controller Interface specification release 1.0 · Compliant with protocol enhancement as defined in P1394a draft 2.0 · Modular 32-bit host interface compliant to PCI Specification release 2.1 · Supports PCI-Bus Power Management Interface Specification release 1.0 · Supports Cardbus · Equipped CIS register · Cycle Master and Isochronous Resource Manager capable · Compatible to PHY Layer implementation of 100/200/400 Mbps via 2/4/8-bit data interface · Built-in FIFOs for isochronous transmit (1024 bytes), asynchronous transmit (1024 bytes), and receive (2048 bytes) · 32-bit CRC generation and checking for receive/transmit packets · 4-isochronous transmit DMAs and 4-isochronous receive DMAs supported · Support both IEEE1394-1995 compliant PHY and P1394a compliant PHY · Internal control and operational registers direct-mapped to PCI configuration space · 2-wire Serial EEPROMTM interface supported
ORDERING INFORMATION
Part number Package 100-pin plastic TQFP (Fine pitch) (14 x 14)
µPD72862GC-9EU
The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability and additional information.
Document No. S14265EJ2V0DS00 (2nd edition) Date Published December 1999 NS CP (K) Printed in Japan
The mark 5 shows major revised points.
1999
µPD72862
FirewardenTM ROADMAP
Firewarden Series PC Application
1 Chip OHCI+PHY µPD72870A 1 Chip OHCI+PHY µPD72870 800M/1.6G p1394.b Link µPD7286x
OHCI Link µPD72862
IEEE1394-1995 Core Development
OHCI Link µPD72861 OHCI Link µPD72860
Hotline Link
1997
1998
1999
2000
2001
2
Data Sheet S14265EJ2V0DS00
µPD72862
BLOCK DIAGRAM
Serial ROM Interface PCI Bus / Cardbus Interface
PCI Controller Interface (Master, Parity Check & Generator) Byte Buf Swap
PCI-DMA
IOREG
CSR (CIS)
PFCOMM
Byte Swap ATF Byte Swap ITF
PCICFG
ATDMA PAU GRSU
ITCF
Byte RF Swap RCF
Link Layer Core
OPCIBUS_ARB
GRQU ITDMA IRDMA0IRDMA3 SFIDU
IOREG
ATDMA ATF CIS CSR IOREG IRDMA ITCF ITDMA ITF OPCIBUS_ARB PAU PCICFG PCIS_CNT PFCOMM RCF RF SFIDU
: Asynchronous Transmit DMA : Asynchronous Transmit FIFO : CIS Register : Control and Status Registers : IO Registers : Isochronous Receive DMA : Isochronous Transmit Control FIFO : Isochronous Transmit DMA : Isochronous Transmit FIFO : OPCI Internal Bus Arbitration : Physical Response and Request Unit : PCI Configuration Registers : PHY Control Isochronous Control : Pre Fetch Command FIFO : Receive Control FIFO : Receive FIFO : Self-ID DMA
PHY/Link Interface
OPCI Internal Bus PCIS Bus (PCI Slave Bus) PCIS_CNT
Data Sheet S14265EJ2V0DS00
3
Others parts begin by up
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