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Details, datasheet, quote on part number:UPD72871F1-FA2
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Datasheet text preview:
PRELIMINARY DATA SHEET
µPD72870,72871
IEEE1394 1-CHIP OHCI HOST CONTROLLER
MOS INTEGRATED CIRCUIT
The µPD72870, 72871 are the LSIs which integrated OHCI-Link and PHY function into a single chip. The µPD72870, 72871 comply with the P1394a draft 2.0 specifications and the OpenHCI IEEE1394 1.0 and work up to 400 Mbps. These make design so compact for PC and PC card application.
FEATURES
· Compliant with Link Layer Services as defined in 1394 Open Host Controller Interface specification release 1.0 · Compliant with Physical Layer Services as defined in P1394a draft 2.0 (Data Rate 100/200/400 Mbps) 3-port : µPD72870 1-port : µPD72871 · Compliant with protocol enhancement as defined in P1394a draft 2.0 · Modular 32-bit host interface compliant to PCI Specification release 2.1 · Support PCI-Bus Power Management Interface Specification release 1.0 · Modular 32-bit host interface compliant to Card Bus Specification · Cycle Master and Isochronous Resource Manager capable 5 · Built-in FIFOs for isochronous transmit (1024 bytes), asynchronous transmit (1024 bytes), and receive (2048 bytes) · 32-bit CRC generation and checking for receive/transmit packets · 4 isochronous transmit DMAs and 4 isochronous receive DMAs supported · 32-bit DMA channels for physical memory read/write · Clock generation by 24.576 MHz X'tal · Internal control and operational registers direct-mapped to PCI configuration space · 2-wire Serial EEPROMTM interface supported · Separate power supply Link and PHY
ORDERING INFORMATION
Part number Package 160-pin plastic LQFP (Fine pitch) (24 x 24 mm) 192-pin Plastic FBGA (14 x 14 mm) 160-pin plastic LQFP (Fine pitch) (24 x 24 mm) 192-pin Plastic FBGA (14 x 14 mm)
µPD72870GM-8ED µPD72870F1-FA2 µPD72871GM-8ED µPD72871 F1-FA2
The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability and additional information.
Document No. S13925EJ2V0DS00 (2nd edition) Date Published September 1999 NS CP(K) Printed in Japan
The mark 5 shows major revised points.
1999
µPD72870,72871
BLOCK DIAGRAMS
Top Block Diagram Serial ROM Interface
PCI Bus/ Cardbus
Link
PHY
Cable Interface
PHY Signal
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Preliminary Data Sheet S13925EJ2V0DS00
µPD72870,72871
PHY Block Diagram
PH Y Control Signal (CMC,P C0-PC 2)
C able Port1
Arbitr ation and Control State Machine Logic PH Y/Link Interfac e Link Interfac e I/O
C able Port2
C able Interfac e
C able Port3
R ec eive Data D ec oder and R etimer
Voltage and Curr ent Gener ator PH Y Signal
Trans mit Data Enc oder C able P ower Status
Cr ystal Oscillator PLL System and Trans mit Clock Gener ator
Remark
Cable Port:
Preliminary Data Sheet S13925EJ2V0DS00
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