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Details, datasheet, quote on part number:UPD78053A
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Datasheet text preview:
DATA SHEET
MOS INTEGRATED CIRCUIT
µPD98401A
ATM SAR CHIP
DESCRIPTION
The µPD98401A (NEASCOT-S15TM) is a high-performance SAR chip that segments and reassembles ATM cells. This chip can interface with an ATM network when it is included in a workstation, computer, front-end processor, network hub, or router. The µPD98401A conforms to the ATM Forum Recommendation, and provides the functions of the AAL-5 SAR sublayer and ATM layer. The µPD98401A is compatible with its predecessor, µPD98401, in terms of hardware and software. Functions are explained in detail in the following User's Manual. Be sure to read this manual when designing your system.
µPD98401A User's Manual: S12054E
FEATURES
· Conforms to ATM Forum · AAL-5 SAR sublayer and ATM layer functions · Hardware support of AAL-5 processing · Processing of non-AAL-5 traffic (AAL-3/4 cell, OAM cell, RM cell) by software with raw cell processing function · Hardware support of comparison/generation of CRC-10 for non-AAL-5 traffic · Supports up to 32K virtual channels (VC) · Provided with 16 traffic shapers that carry out transmission scheduling (control of average rate/peak rate) so as to set different transmission rate for each VC · Interface and commands for controlling PHY device · Employs "UTOPIA interface" as cell data interface with PHY device - Octet-level handshake - Cell-level handshake · 32-bit general-purpose bus interface · High-speed DMAC (supports 1-, 2-, 4-, 8-, 12-, and 16-word burst) · JTAG boundary scan test function (IEEE1149.1) · CMOS technology · +5 V single power source Remark In this document, an active low pin is indicated by ×××_B (_B after a pin name).
The information in this document is subject to change without notice.
Document No. S12100EJ3V0DS00 (3rd edition) Date Published February 1999 N CP(K) Printed in Japan
The mark
shows major revised points.
©
1997
µPD98401A
ORDERING INFORMATION
Part Number Pac k age 208-pin plastic QFP (fine pitch) (28 × 28 mm)
µPD98401AGD-MML
SYSTEM CONFIGURATION
ATM interface card
Reception
µ PD98401A
Control memory
µ PD98402A
PMD Transmission
ATM network
Bus interface
I/O bus
BLOCK DIAGRAM
Receive data FIFO
PHY interface reception block
PHY device transmission block
Reception controller
System port
DMA controller and host interface
Sequencer
Control memory interface
Control memory
Transmission controller PHY interface transmission block PHY device reception block
Transmit data FIFO (10 cells)
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Data Sheet S12100EJ3V0DS00
µPD98401A
PIN CONFIGURATION
Rx7-Rx0 RCLK RENBL_B RSOC PHY interface EMPTY_B/RxCLAV Tx7-Tx0 TCLK TENBL_B TSOC FULL_B/TxCLAV PHRW_B PHOE_B PHCE_B PHINT_B AD31-AD0 PAR3-PAR0 OE_B SIZE2-SIZE0 DR/W_B ATTN_B GNT_B Bus interface RDY_B ABRT_B ERR_B SR/W_B SEL_B ASEL_B CLK RST_B INTR_B Slave Master
CD31-CD0 CPAR3-CPAR0 CA17-CAD CWE_B COE_B CBE_B3-CBE_B0 INITD Control memory interface
DBVC DBMD DBML DBMF DBMR Bus monitoring
JDO JDI JCK JMS JRST_B JTAG boundary scan interface
TRF_B
Test pin (fixed to low level)
VDD VDD GND Power supply
Data Sheet S12100EJ3V0DS00
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