|
Details, datasheet, quote on part number:UPD9611
| |
Datasheet text preview:
PRELIMINARY DATA SHEET
MOS INTEGRATED CIRCUIT
µPD9611
FOUR-CHANNEL PCM CODEC
The µPD9611 incorporates 4-channel A-law/µ-law PCM CODECs compliant with ITU-T Recommendation G.711/ G.714 and is suitable for applications such as PBX analog subscriber line circuits. Its gain setting circuit allows transmit/receive gain to be set for 4 channels independently by externally inputting digital signals.
FEATURES
· · · · · · · · · ·
Single-chip CMOS monolithic LSI ITU-T Recommendation G.711/G.714 compliant Four-channel PCM CODECs integrated on a single chip Compatible with A-law and µ-law Digital gain setting for each channel · Transmit : +7.5 to 8.0 dB (0.5 dB step) · Receive : 0 to 15.5 dB (0.5 dB step) Data transfer system: Transmit/receive synchronization Data rate: 2048 kHz +5 V single power supply Power down function for each channel Low power consumption
ORDERING INFORMATION
Part Number Package 48-pin shrink SOP (375 mil)
µP D 9 6 1 1 G T
The information in this document is subject to change without notice. Document No. S11018EJ2V0DS00 (2nd edition) Date Published October 1996 P Printed in Japan
©
1996
µPD9611
PIN CONFIGURATION (Top View)
48-pin shrink SOP (375 mil)
AIN1 AOUT1 NC AIN2 AOUT2 NC ACOMIN1 ACOMOUT1 ACOMIN2 ACOMOUT2 AVDD1 AVDD2 AVDD3 AVDD4 DVDD NC PD1 PD2 PD3 PD4 FSC DCLK DX DR
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
AIN4 AOUT4 NC AIN3 AOUT3 NC ACOMIN3 ACOMOUT3 ACOMIN4 ACOMOUT4 AGND1 AGND2 AGND3 AGND4 SUBGND DGND NC NC NC RST LAW SPDATA SPSYNC SPCLK
µPD9611GT
DX FSC LAW NC RST
A C O M IN1 - A C O M IN4 AGND1-AGND4 A IN1 - A IN4 A OUT1 - A OUT4 A V D D1 - A V D D 4 DCLK DGND DR D V DD
: A n a l o g common voltage in : A n a l o g ground : A n a l o g signal in : A n a l o g signal out : A n a l o g power supply : D a t a clock in : D i g i t a l ground : R e c e i v e PCM data in : D i g i t a l power supply
: T r a n s m i t PCM data out : F r a m e synchronous clock in : A - l a w / µ - l a w control in : N o connection : R e s e t in : S e r i a l port data clock in : S e r i a l port data in : S e r i a l port synchronous clock in
A C O M OUT1 - A C O M OUT 4 : A n a l o g common voltage out
P D 1 - P D 4 : P o w e r down control S PCLK S PDATA S PSYNC
S U B G N D : S u b ground
2
µPD9611
BLOCK DIAGRAM
AVDD1
AVDD2
AVDD3
AVDD4
DVDD
CH1 AIN1 AOUT1 A/D D/A
APD1 AIN2 AOUT2
ACOMIN1 CH2
DSP Channel FiIter
APD2
ACOMIN2
AIN3 AOUT3
CH3 DX APD3 ACOMIN3 DR RST
AIN4 AOUT4
CH4 I/O Linear A, µ DGS MUX, DEMUX APD1 APD2 APD3
SPSYNC SPCLK SPDATA LAW PD1 PD2 PD3 PD4
APD4
ACOMIN4
ACOMIN1 ACOMOUT1 ACOMIN2 ACOMOUT2 ACOMIN3 ACOMOUT3 ACOMIN4 ACOMOUT4 Voltage Reference
APD4
Clock Generator
FSC DCLK
AGND1
AGND2
AGND3
AGND4
DGND
SUBGND
3
|
|
