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Details, datasheet, quote on part number:UPD98401
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| Part: | UPD98401 |
| Category: | Communication => Network => ATM (Asynchronous Transfer Mode) => ATM/SMDS/Frame Relay |
| Description: | Sar And Atm Layer Controller |
| Company: | NEC Electronics Inc. |
| Datasheet: | Download UPD98401 datasheet File size : 31 kB |
| Request For quote: | Find where to buy UPD98401
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Datasheet text preview:
µ P D 9 8 4 0 1 A S A R A N D AT M L A Y E R C O N T R O L L E R
The µPD98401A is a high-performance Asynchronous Transfer Mode (ATM) controller that implements ATM protocol layer and adaptation layer (AAL) functions with an advanced architecture optimized for minimal host CPU and I/O bus utilization. The µPD98401A integrates a 32-bit DMA controller for bus master operations and an efficient buffer management scheme for reduced buffer memory requirement, and also provides CRC-10 generation and verification for AAL-3/4 and OAM cells. The µPD98401 performs all AAL-5 functions, including segmentation and re-assembly (SAR). The segmented data, based on the various ATM adaptation types, is processed by the µPD98401A into ATM cells.
BLOCK DIAGRAM
Receive Data FIFO
Receive PHY Interface
Receive PHY
Receive Controller
System Port
DMA Controller and Host Interface
Sequencer
Control Memory Interface
Control Memory
Transmit Controller
Transmit Data FIFO
Transmit PHY Interface
Transmit PHY
F E AT U R E S · ATM layer and AAL functions compliant with ITU-TS standard and ATM Forum specifications · Full AAL-5 support for implementing other ATM adaptation types · Up to 32K active virtual channels for high-end server applications · Traffic shaping using dual leaky bucket scheduling algorithms; traffic handling based on specified priority level, specified average, and peak traffic rates · Extremely flexible buffer management scheme for efficient utilization of memory space · Integrated FIFOs for receive and transmit cell buffering · Re-assembly timer to terminate buffering of received cells associated with an erroneous frame
HOST INTERFACE · Generic 32-bit multiplexed address/data bus interface for simple connection to popular I/O buses (PCI, SBus, GIO, APbus) with minimal glue logic · Up to 33-MHz operation with separate control signals for bus master and slave operations · High-performance DMA controller with programmable burst mode capability · Big Endian and little Endian formats · Four mail boxes that inform the host CPU of completed frame transmission and reception and reduce CPU interruptions · Scattering and gathering of data into and out of host memory for more efficient CPU utilization · Flexible architecture with no restriction on transmit buffer size or the number of entries that may be used · Up to 32 free buffer pools with flexible buffer sizes for received traffic
levels. The µPD98401A incorporates 16 shapers using the dual leaky bucket algorithm for traffic management. The host specifies an associated shaper for each active channel. Each shaper has a priority level, an average traffic rate, and a peak rate. These parameters are supplied to a set of internal shaper registers by the host and may be modified at any time to allow for flexible traffic flow control.
TRANSMIT QUEUES The transmit queues consist of multiple packet descriptors associated with various active connections. A single packet may reside in one or more buffers. The read pointer of the transmit queue resides in a transmit VC table located in control memory. Its initialization is done by the host and then modified by the µPD98401A each time it fetches a new data segment for transmission. A packet descriptor may contain either a pointer to a data buffer or, in the case of multiple buffers per packet, a pointer to a packet directory. The µPD98401A stores the read address and the remaining size of the active buffer for each connection in the transmit VC table. This mechanism limits access to the transmit queue and/or packet directory to when a new data buffer is needed.
MEDIA INTERFACE · UTOPIA interface for direct connection to the readily available physical interface devices, such as NEC's µPD98404 SONET/SDH framer chip · Information transfers between the host CPU and NEC's µPD98404 SONET/SDH framer chip using its host interface, eliminating the need for separate signaling between the host and the framer chip
RECEIVED QUEUES Received traffic is stored in buffers in system memory. The host supplies 32 pools of free buffer descriptors. Each pool consists of link-list batches of free buffer descriptors. Each batch consists of one or more buffer descriptors and ends with a batch link pointer. An entry in the VC table instructs each VC of its assigned pool. The buffer sizes are flexible and may range from 64 bytes to 64K bytes.
GENERAL · Loopback of transmit traffic to the receiving direction at the UTOPIA (PHY) interface side · Access pins for self-testing · JTAG boundary scan option for automatic testing · Low-power CMOS technology (0.8-micron) · 208-pin PQFP package
T R A N S M I T O P E R AT I O N After the scheduler selects the channel to be served, the transmit operation begins by fetching a segment of the packet from system memory. The µPD98401A transmit circuitry constructs an ATM cell by tagging header information, excluding the HEC, to the fetched data segment. The header information is based on data retrieved from the VC table. The cell is then staged in the integrated transmit FIFO until ready to be transferred to the physical interface device. The transmit circuitry is responsible for maintaining relevant information on the currently active transmit buffer in the VC table. When a buffer is exhausted, the transmit circuit fetches a new number from system memory and places all necessary information in the VC table. The transmit circuitry deactivates a channel when its transmit queue is exhausted.
A P P L I C AT I O N S · ATM adapter cards · Internetworking devices (bridges and routers) · Workstations and servers
TRAFFIC MANAGEMENT AND CONTROL The µPD98401 supports a maximum of 32,000 active virtual channels (VCs). Scheduling of data flow from the various active channels is done by an on-chip scheduler according to the channel's traffic shaping parameters and prority
R E C E I V E O P E R AT I O N When an ATM cell is received, the µPD98401A receive circuitry verifies whether the cell belongs to one of the selected receive channels by comparing the cell's VPI/VCI field against a lookup table maintained in control memory. If a match is successful, the cell is directed to an integrated receive FIFO. The receive circuitry reads the channel corresponding entries off the VC table. If this is the first received cell of a packet and no buffer descriptors have been assigned or the buffer has been exhausted, the receive circuitry fetches a new batch of free buffer descriptors and then moves the received data (cell without the header) into the buffer location in system memory pointed to by the first descriptor. The receive circuitry increments the write pointer and updates the CRC and the packet length entries. Upon receiving a cell with end-of-packet indication, the receive circuitry verifies the packet length and the CRC calculation with the value embedded in the last cell, writes a receive indication and error information into a receive mailbox in system memory, and sends an interrupt (if enabled) to the host.
AT M S Y S T E M A R C H I T E C T U R E
µPD98401A
µPD98404
Video
Data Adaptation Layer ATM Layer Physical Layer Voice Data Video
Voice
98YL-0166B (6/98)
T Y P I C A L AT M N E T W O R K I N T E R FA C E C A R D ( AT M - N I C )
Control Memory
S-Bus/ PCI/ VME/ Others
Bus I/F
ATM Controller µPD98401A
ATM/SONET PHY µPD98404
PHY I/F
Fiber or UTP
98YL-0167B (6/98)
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