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Details, datasheet, quote on part number:NC1503_VISoc
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Datasheet text preview:
NEURICAM S.p.A. Via S. Maria Maddalena, 12 - 38100 Trento - Italy Tel. +39 0461 260552 Fax. +39 0461 260617 email: info@neuricam.com - http:\\www.neuricam.com
VISoc Datasheet
Rel. 08/03
Authors ID Project Name Date Revision Status Approved by Number of Pages Scope / Overview
Filippo Cioni, Daniele Covi VISoc 08 / 04 / 2003 Rel 08-03 Official, Preliminary Alvise Sartori, Pietro Chiesa, Marco Galluppi 128 Customer documentation of the VISoc chip. It includes a description from hardware and software point of view. It contains a detailed description of the communication protocols and registers accessible to the host controller. The functionalities of the RISC processor are described in the software section. The TOTEM and digital camera functionalities are explained during their corresponding register description in the hardware part Rel. 08-03 Date Pages 08 / 04 / 2003 128 Description of changes Official Release
Record of revisions
Disclaimer
Information furnished by NeuriCam is believed to be accurate and reliable. However, no responsibility is assumed by NeuriCam for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of NeuriCam. NeuriCam does not assume any responsibility for use of any circuitry described, and NeuriCam reserves the right at any time without notice to make corrections, modifications, enhancements, improvements, and other changes to the said circuitry and specifications. NeuriCam assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using NeuriCam components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. NeuriCam's products are not authorized for use as critical components in life support devices or systems without the express written approval of NeuriCam. As used herein: 1. Life support devices or systems are devices or systems which are intended for surgical implant into the body, or support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. ESD WARNING! ESD (Electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although VISoc features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
VISoc Datasheet Index 1 2 3
NeuriCam
General Description ........ 7 Key Features and Applications ...... 9 Pin Configuration ......... 10 3.1 Alphabetical Order Pin list .......... 10 3.2 Numerical Order Pin List ... 13 3.3 Pinout and Floorplan .......... 14 4 Detailed Block Description....15 4.1 Power on Reset Block ........ 17 4.2 Loader ........ 18 4.3 VISoc Digital Camera ........ 19 4.4 Camera Controller (DMA channel)............21 4.5 SSRAM and FLASH Controller........24 4.5.1 Synchronous Access .... 25 4.5.2 Asynchronous Access..25 4.6 Neural DSP: TOTEM and Interpolating LUTs ......... 26 4.6.1 TOTEM Core Architecture.........28 4.6.2 Barrel Shifter ...... 30 4.6.3 Interpolating Look-Up Tables .... 31 4.6.4 The Reactive Tabu Search Training Algorithm...........33 4.7 RISC Processor ......... 34 4.7.1 Introduction to Programmers......34 4.7.1.1 Core Register Set .. 34 4.7.1.2 Auxiliary Register Set..........35 4.7.1.3 RISC Memory Map ............. 35 4.7.1.4 Instruction Set Summary......36 4.7.2 Data Organization And Addressing Mode..........37 4.7.3 Instruction Format ....... 39 4.7.4 Interrupts.............40 4.7.4.1 ILINK Register ..... 40 4.7.4.2 Interrupt Vectors ... 40 4.7.4.3 Interrupt Enables...40 4.7.4.4 Returning From Interrupts ............ 41 4.7.4.5 Hardware Interrupt Generators ..... 41 4.7.4.5.1 Reset ....... 41 4.7.4.5.2 Memory Error .. 41 4.7.4.5.3 Instruction Error ............. 41 4.7.4.6 Interrupt Times ..... 41 4.7.5 Condition Code Field...42 4.7.5.1 Condition Code Register......42 4.7.5.2 Condition Codes ... 42 4.7.6 Instruction Set Details .......... 43 4.7.6.1 Arithmetic and Logical Operations........43 4.7.6.2 Single Operand Instructions..........44 4.7.6.2.1 The Breakpoint Instruction ...... 45 4.7.6.2.2 The Sleep Instruction......46 4.7.6.3 Jump, Branch and Loop Operations............46 4.7.6.4 Load and Store Operations............47 4.7.6.5 Multiple Shift Operations .... 48 4.7.6.6 AVER Instruction .......... 48 4.7.7 The Zero Overhead Mechanism .......... 50 4.7.7.1 Single Instruction Loops......51 4.7.7.2 Loop Count register .....
........ 51 4.7.7.3 Branch And Jumps In Loops.........52 4.7.7.4 Instructions With Long Immediate Data In Loops ........ 52 4.7.8 Instruction Pipelining .. 54 4.7.8.1 Long Immediate Operands............55 4.7.8.2 Conditional Instruction Timing.....55 4.7.8.3 Jump and Branch Timings ............ 56 4.7.9 The I-Cache Structure and Organization ............ 58 Rel 08-03 Preliminary Page 3 / 128
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