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Details, datasheet, quote on part number:NC3003
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Datasheet text preview:
Via Santa Maria Maddalena 12, 38100 Trento, Italy tel. +39-0461-260 552 - fax + 39-0461-260 617 e-mail: info@neuricam.com; http: www.neuricam.com
NC3003 TOTEM Digital Processor for Neural Networks
DATA SHEET Rel. 12/99 General features
The NC3003 is a digital VLSI parallel processor for fast learning and recognition with artificial neural networks in applications where a high throughput of recognition is required. Its architecture (see Fig. 1) is optimised for the implementation of the "Reactive Tabu Search" learning algorithm, a competitive alternative to back-propagation which does not require derivatives of the transfer function and is ideally suited for VLSI implementation. Its main features are summarised below: · Pipelined Digital Data Stream, Single Instruction Multiple Data (SIMD) architecture optimised for the execution of the multiply-accumulate operation: Acc(n+1) := Acc(n) + DataIn * Weight (n) in a single clock cycle in parallel on 32 fast processing units · · 32 fixed-point fully-parallel multiply-and-accumulate processors (MACs) operating in parallel from a common broadcast bus. 2' complement data format s 64-Kbit internal dynamic random-access memory organised as 32 blocks of 256×8 bits for weight storage with close coupling with processors. Memory can be assigned either to a single neuron or be partitioned among several neurons to implement multi-layer networks with a single chip. Refresh is transparent to the user. Limited word width for economical layout: 16-bit data, 8-bit weight, 32-bit results 32-input, 16-output barrel shifter for scaling of results to 16-bit interface Performance of 750 million multiply-and-accumulate operation per second with a 25 MHz clock. A multi-layer perceptron with a 64-128-64 topology suitable to solve the target application can be evaluated in about 10 µs by two NC3003 chips operating in parallel. Higher performance can be achieved by paralleling up to four chips per network level to implement neurons with up to 256 inputs Simple SRAM-like interface with data input, data output and address buses and control lines. Evaluation boards for PCI and CompactPCI buses are available, including software drivers and graphical tools under Windows NT and Linux. Support circuitry for four external 16-input, 16-output look-up tables (LUT) implemented in static RAM to calculate the activation function of the neural network Compact chip size and limited pin count for ease of interfacing and low system cost 100-pin PQFP plastic package
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Rel. 12/99
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NC3003
NeuriCam
Enhancements with respect to the NC3001
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Weight depth of 256 bytes Synchronous loading input instructions Loadable memory, oputput and LUT pointers Sequential weight memory write mode Improved user interfase with internal configuration and instruction registers Bypass mode for LUT loading Auxiliary register for external LUT control l6-bit output bus All TTL level input pins 3.3 V interface mode, 5 V internal operating voltage
Rel. 12/99
2
NC3003
NeuriCam
Number of processors Total on-chip RAM Processing power Clock frequency Sustained input rate Latency Die size No. of transistors Power consumption Package
32 64 Kbit 750 million MAC operations per second 25 MHz 1 input/clock cycle 3 clock cycles 40 mm2 350.000 1 W @ 5V and 25 MHz 100-pin plastic PQFP
Table 1. Chip characteristics
4 VDDI VSSI VDDE VSSE AUXILIARY REGISTER E_AUX E_DOUT
DOUT [15:0] 16 16 MUX 16 BARREL SHIFTER 16 LATCH 32 32
BYPASS_ADDR
CTRL_LUT
BARREL SHIFTER REGISTER MUX
EN_DOUT
BYPASSN ADDR
AUX [3:0]
OUTPUT BUS 32
INCR_LUT
ADDRESS LUT GENERATOR LD_OUTREG OUTPUT ADDR GENERATOR CL_ACC 256 x 8 DRAM WR_MEM 8 INTERNAL CONTROL BUS 16
BROADCAST BUS WEIGHT BUS WEIGHT ADDRESS BUS
32 OUTPUT REGISTER 32 16 x 8 MAC 256 x 8 DRAM
32 OUTPUT REGISTER 32 16 x 8 MAC
TP_TEST TP_WR TP_WRITE TP_WRITE_CYC TP_MEM_RD
(x32)
8
8
8
16
CLK CSN1 CSN2 WRN RDN REFRESHN RESETN
CONFIGURATION REGISTER COMMAND REGISTER
13 8 MUX SEL_WR GRAY
8 MUX 16
WEIGHT ADDR GENERATOR FOR CALCULATE
WEIGHT ADDR GENERATOR FOR SEQ WRITE
GRAY TO BIN DECODER
MAC INPUT REGISTER
Fig. 1. Block diagram of 32-processor NC3003 chip
Rel. 12/99
DIN [15:0]
A [15:0]
3
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