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Details, datasheet, quote on part number:NJU3754V
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Datasheet text preview:
NJU3754
PRELIMINARY
11-BIT PARALLEL TO SERIAL CONVERTER
GENERAL DESCRIPTION
The NJU3754 is an 11-bit parallel to serial converter especially applying to MCU input port expander. It can operate from 2.7V to 5.5V. The NJU3754 requires only 3-port of MCU for data transmission and realizes the effective input port assignment. The status of the input ports is output through a latch circuit, a shift register and a 3-state buffer as the serial data synchronizing with the serial clock. The hysteresis input circuit of the serial clock terminal realizes 5MHz and more operation. Furthermore, pull-up resistors on chip of P0 to P10 terminals reduce external components for key-scan circuit, etc.
PACKAGE OUTLINE
NJU3754V
FEATURES
11-Bit Parallel In Serial Out 3-line Serial Interface Output Hysteresis Input 0.5V typ at 5V Maximum Operating Frequency 5MHz and more Operating Voltage 2.7 to 5.5V C-MOS Technology Package Outline SSOP16
PIN CONFIGURATION
P0 P1 P2 P3 P4 P5 P6 VSS 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VDD CE CLK SO P10 P9 P8 P7
BLOCK DIAGRAM
VSS P0 P1
Shift Register Latch Circuit
VDD SO
P2
P9 P10
Control Circuit
CE CLK
Ver.2004-03-15
-1-
NJU3754
TERMINAL DESCRIPTION
No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 SYMBOL P0 P1 P2 P3 P4 P5 P6 VSS P7 P8 P9 P10 SO CLK CE VDD I/O I I I I I I I I I I I O I I FUNCTION
Parallel Data Input Terminals (with pull-up resistors)
Ground Parallel Data Input Terminals (with pull-up resistors) Serial Data Output Terminal Serial Clock Input Terminal Chip Enable Input Terminal Power Supply Terminal (2.7 to 5.5V)
FUNCTIONAL DESCRIPTION
At the falling edge of CE terminal, the status of P0 to P10 terminal is latched and transferred to the shift register. At the mean time, the P0 data is output from SO terminal. While CE terminal is "L", the data from P1 to P10 in the shift register are synchronized with the falling edge of CLK terminal and output from SO terminal. When CE terminal is "H", SO terminal is high impedance.
Note 1) If the 11th falling edge and later are input to CLK terminal while CE is "L", the 12th and the following data are invalid. CE CLK SO P0~P10
Valid P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 Invalid
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Ver.2004-03-15
NJU3754 NJU3555
ABSOLUTE MAXIMUM RATINGS
(Ta=25°C) PARAMETER Supply Voltage Range Input Voltage Range Power Dissipation Operating Temperature Range Storage Temperature Range SYMBOL VDD VI PD Topr Tstg RATINGS -0.3 ~ +7.0 VSS-0.3 ~ VDD+0.3 300 (SSOP) -40 ~ +85 -65 ~+150 UNIT V V mW °C °C
Note 2) All voltage are relative to VSS=0V reference. Note 3) Do not exceed the absolute maximum ratings, otherwise the stress may cause a permanent damage to the IC. It is also Note 4)
recommended that the IC is used in the range specified in the DC electrical characteristics, or the electrical stress may cause malfunctions and impact on the reliability. To stabilize the IC operation, place decoupling capacitor between VDD-VSS.
DC ELECTRICAL CHARACTERISTICS
PARAMETER Operating Voltage Operating Current SYMBOL VDD ID D VIH VIL IIH IIL1 IIL2 VOH VOL ITSL VDD=5V, VI=5V P0~P10, CLK, CE Terminals VDD=5V, VI=0V CLK, CE Terminals VDD=5V, VI=0V P0~P10 Terminals IOH=-0.4mA IOL=+3.2mA SO Terminal CE=H SO Terminal VDD=5.5V P0~P10=Open CE=H, CLK=L SO=No load P0~P10, CLK, CE Terminals (VDD=2.7~5.5V, VSS=0V, Ta=25°C, unless otherwise noted) CONDITION MIN TYP MAX UNIT 2.7 0.7VDD VSS -1 -100 VDD-0.4 VSS -2 -40 5.5 10 VDD 0.3VDD 1 -15 VDD 0.4 2 V µA V V µA µA µA V V µA
Input Voltage High-level Input Current Low-level Input Current 1 Low-level Input Current 2 Output Voltage 3-State Leakage Current
Ver.2004-03-15
-3-
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