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Details, datasheet, quote on part number:NJU8402M
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Datasheet text preview:
NJU8402
DIGITAL TO ANALOG CONVERTER FOR STEREO AUDIO
s GENERAL DESCRIPTION
The NJU8402 is a 16-bit delta-sigma Digital-to-Analog Converter for stereo audio. It consists of Serial Audio Data Interface, Digital Interpolation Filter, Modulator, SC LPF, Buffer Amp, System Controller for status control. It operates on single +5V power supply. Furthermore, it accepts 16-bit input audio data length or 18-bit, and supports I2S serial data format and LSB justified. Therefore, the NJU8402 is suitable for CD, MD, DAT and other digital audio applications.
PRELIMINARY
s PACKAGE OUTLINE
NJU8402D
NJU8402M
s FEATURES
q q q q q q q q type 1bit stereo DAC Sample Rate ( fs ) : 50kHz ( Maximum ) Signal-to-Noise Ratio : 94dB Input Audio Data Length : 16bits or 18bits Single ended Analog Output Internal SC type Low Pass Filter Operating Voltage +5V ±5% Package Outline DIP16 / DMP16
s PIN CONFIGURATION
VDD MCKI SCK DATA REQ AOUTL VCOML AVDD 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VSS BCLK LRCK DIN RST AOUTR VCOM AVSS
s BLOCK DIAGRAM
DIN BCLK LRCK Serial Audio Data Interface
Digital Interpolation Filter
Modulator Modulator
SC LPF SC LPF
LPF
AOUTL VCOML
LPF
AOUTR VCOMR
System Controller
SCK REQ MCKI RST DATA
VSS
AVDD
AVSS
VDD
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NJU8402
s TERMINAL DESCRIPTION
PIN No. 1 16 8 9 2 13 14 15 SYMBOL VDD VSS AVDD AVSS MCKI DIN LRCK BCLK INPUT /OUTPUT I I I I FUNCT ION Digital Power Supply, +5V Digital GND, 0V Analog Power Supply, +5V Analog GND, 0V Master Clock Input Terminal The input signal frequency is 256 times or 384 times of fs. Serial Audio Data Input Terminal L/R Channel Clock Input Terminal This clock must synchronize with MCKI. Audio Serial Data Clock Input Terminal This clock must synchronize with MCKI. Control Register Serial Data Sift Clock Input Terminal Control register leads the control data synchronizing the rising edge of SCK signal. When the control register is not used, the state of SCK terminal has to keep level "H". Control Register Serial Data Input Terminal Input data sets various functions. W hen the control register is not used, the state of DATA terminal has to keep level "H". Control Register Serial Data Request Input Terminal The control data are latched in the control register at the rising edge of REQ signal. W hen the control register is not used, the state of REQ terminal has to keep level "H". Reset "L" level signal into reset terminal initializes the system. Left channel Analog Signal Common Terminal for Connecting Smooth Capacitor A chemical capacitor should be connected between this terminal and AVSS for stabilizing. Right Channel Analog Signal Common Terminal for Connecting Smooth Capacitor A chemical capacitor should be connected between this terminal and AVSS for stabilizing. L-Channel Analog Signal Output Terminal R-Channel Analog Signal Output Terminal
3
SCK
I
4
DATA
I
5
REQ
I
12 7 10 6 11
RST VCOML VCOMR AOUTL AOUTR
I O O
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NJU8402
s FUNCTION DESCRIPTION
(1-1) Analog Audio Signal Output Analog signal output is biased in the chip and the maximum amplitude is 0.56 × AVDD. The internal switched capacitor Low Pass Filter is so effective that the external Low Pass Filters are required only 2pole LPF or 3-pole.
(1-2) Serial Data Interface DIN (Data Input), BCLK (Bit Clock) and LRCK (L/R Clock) are the serial data interface terminals. BCLK is the bit clock of audio data and IO data are leaded at raising edge of the BCLK. The signal into LRCK terminal represents the signal for distinguishing between Lch and Rch, and the signal for starting data. The frequency of LRCK is sampling rate of system ( fs ). The MCIK must be synchronized with LRCK and is 256 times or 384 of fs. The serial data format is complement of 2, MSB-first and compatible with I2S serial data protocol or LSB justified. This serial data format is set by the control register. LRCK Left Right Channel
BCLK
DIN
15 14 13
10
15 14 13
10
I2S serial data format
LRCK
Left
Right Channel
BCLK
DIN
0
15 14
210
15 14
210
LSB justified serial data format
(1-3) System Clock System Clock into the MCIK terminal must be 256 times or 384 times of fs and synchronizing with LRCK. This frequency is set by the control register.
(1-4) Reset The external reset is the asynchronous reset. Reset is released at the falling edge at LRCK. Reset by command is synchronous which operates as same as the external reset function.
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