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Details, datasheet, quote on part number:NJU8714
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| Part: | NJU8714 |
| Category: | Multimedia => Audio => Decoders => Stereo/Surround Decoders |
| Description: | Stereo BTL Switching Driver For Class D Amplifier |
| Company: | NJR Corporation |
| Datasheet: | Download NJU8714 datasheet File size : 112 kB |
| Request For quote: | Find where to buy NJU8714
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Datasheet text preview:
NJU3555 NJU3555 8714
STEREO BTL OUTPUTS SWITCHING DRIVER FOR Class D AMPLIFIER
GENERAL DESCRIPTION
The NJU8714 is a stereo BTL outputs switching driver for class D amplifier. It receives PWM/PDM signals from DSP outputs, and drives headphones or speakers by BTL outputs. Output drivers are composed of Series-Connected N-channel FETs, and output voltage levels can be controlled by variable power supply with keeping all of input signal information. The NJU8714 incorporates BTL outputs amplifiers, which eliminate AC coupling capacitors. Also, it provides "SEL" terminal which selects "Synchronous" or "Asynchronous". "Asynchronous" can be reduced the operating current. Therefore, it is suitable for portable audio set and others.
PACKAGE OUTLINE
NJU8714VB2
FEATURES
2-channel 1bit Audio Signal Input Stereo BTL Outputs Output Power : Typ.150mW@8 BEEP Function Standby Function Output Driver Control Function Operating Voltage VDD: 1.7V to 2.7V VDDO: 0V to 2.0V VG: 4.5V to 5.25V CMOS Technology Package Outline :SSOP20-B2
PIN CONFIGURATION
MCK VSS HALTB DIN1 BEEPIN OBEEP1 OUT 1 VSSO OUT1X VDDO1 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VDD SEL STBYB DIN2 VG OBEEP2 OUT 2 VSSO OUT2X VDDO2
BLOCK DIAGRAM
VDD VSS VG VDDO1 DIN1
Level Shifter
OUT1
Control Logic Pre Driver
OUT1X
VSSO VDDO2 DIN2 MCK STBYB HALTB SEL BEEPIN OBEEP2
Level Shifter Level Shifter Level Shifter Level Shifter Level Shifter
OUT2
Control Logic Pre Driver
OUT2X
VSSO
OBEEP1
Ver.2004-05-21
-1-
NJU8714
TERMINAL DESCRIPTION
FUNCTION Master Clock Input Terminal Power GND: VSS=0V (Note.1) Output Driver Control Terminal 1bit Data Input Terminal 1 BEEP Signal Input Terminal BEEP Output terminal 1 Positive Output Terminal 1 Output GND terminal: VSS=0V (Note. 1) Negative Output 1 Output Power supply 1(Note. 2) Output Power supply 2(Note. 2) Negative Output 2 Positive Output Terminal 2 BEEP Output terminal 2 Pre-driver Power supply 1bit Data Input Terminal 2 Standby control terminal (L:Standby) Input Signal Synchronization With "MCK" 19 SEL I (H: Synchronous., L: Asynchronous.) 20 VDD Power Supply: VDD=2.5V (Note. 1) Pin No.2(VSS), 8(VSSO) and 13(VSSO) should be connected at the nearest point to the IC. (Note. 2) Pin No.10(VDDO1) and 11(VDDO2) should be connected at the nearest point to the IC. No. 1 2 3 4 5 6 7 8,13 9 10 11 12 14 15 16 17 18 SYMBOL MCK VSS HALTB DIN1 BEEPIN OBEEP1 OUT1 VSSO OUT1X VDDO1 VDDO2 OUT2X OUT2 OBEEP2 VG DIN2 STBYB I/O I I I I O O O O O O I I
INPUT TERMINAL STRUCTURE
VDD
Input Terminal
VSS
MCK, HALTB, DIN1, DIN2, BEEPIN, STBYB, SEL
-2-
Ver.2004-05-21
NJU3555 NJU3555 8714
FUNCTIONAL DESCRIPTION
(1) Signal Output The OUT1/1X and OUT2/2X generate respectively L-channel and R-channel output signals, which will be converted to analog signals via external 2nd-order or higher LC filter. A switching regulator with a high response against a voltage fluctuation is the best selection for the VDDO1 and VDDO2, which are the power supply for output drivers. To obtain better T.H.D. performance, the stabilization of the power is required. (2) Master Clock (MCK) Input 1-bit audio signals such as PWM or PDM to the DIN1 and DIN2 pins. By setting the SEL pin to "H", master clock (MCK) synchronizes the audio signal inputs (DIN1 and DIN2). In case of "SEL" = "L", input signals go into the amplifier circuits by own timing. Therefore, it requires careful design of PCB patterns from DSP to NJU8714. The setup time and the hold time should be kept in the AC characteristics because DIN1 and DIN2 are fetched with the rising edge of MCK. MCK requires jitter-free or jitter as small as possible because the jitter downs S/N ratio. (3) Power Supply VDD : Power supply for input part. VG : Power supply for control logic and pre-driver which drives the transistor gates of output drivers. It requires much higher power supply voltage than VDDO1 and VDDO2 for better T.H.D.. VDDO1, VDDO2 : Power supply for output drivers. (4) Output Control Output circuit is selected by the conditions of STBYB, HALTB, SEL, DIN1, DIN2 and MCK. STBYB L H L H HALTB L H H H SEL * * * L DIN1, DIN2 * * * L H L H MCK * * * * OUT1 VSSO Hi-z VSSO VDDO1 VSSO VDDO1 OUT 2 VSSO Hi-z VSSO VDDO2 VSSO VDDO2 OUT1X VSSO Hi-z VDDO1 VSSO VDDO1 VSSO OUT2X VSSO Hi-z VDDO2 VSSO VDDO2 VSSO
*Don't care BEEP circuit is operated regardless of STBYB and HALTB. (5) Input Signal Synchronization Function DIN1 and DIN2 are synchronized with master clock by setting SEL pin to "H". By setting SEL pin to "L", DIN1 and DIN2 are asynchronous with master clock. (6) Output Driver Control Function By setting HALTB pin to "L", high side output drivers become OFF and Low side output drivers become ON, then both of OUT1/1X and OUT2/2X output VSSO level signals. This function works regardless of STBYB pin setting. (7) Standby Control Function By setting STBYB pin to "L", the NJU8714 becomes standby condition. During standby condition, by setting HALTB to "L", OUT1/1X and OUT2/2X become VSSO, and by setting HALTB pin to "H", OUT1/1X and OUT2/2X become Hi-z. To save the power supply current at standby, MCK requires "L" level.
Ver.2004-05-21
-3-
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