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Details, datasheet, quote on part number:NJU8721V
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| Part: | NJU8721V |
| Category: | Multimedia => Audio => Amplifiers => Power Amplifiers => Class D Amplifier |
| Description: | Class D Headphone Amplifier For Digital Audio |
| Company: | NJR Corporation |
| Datasheet: | Download NJU8721V datasheet File size : 160 kB |
| Request For quote: | Find where to buy NJU8721V
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Datasheet text preview:
NJU8721
PRELIMINARY
CLASS D HEADPHONE AMPLIFIER FOR DIGITAL AUDIO
! GENERAL DESCRIPTION
The NJU8721 is a class D Headphone Amplifier th featuring 6 modulation. It includes Digital Attenuator, Mute, and De-emphasis circuits. It converts digital source input to PWM signal output which is converted to analog signal with simple external LC low-pass filter. The NJU8721 realizes very high power-efficiency by class D operation. Therefore, it is suitable for portable audio set and others.
! PACKAGE OUTLINE
NJU8721V
! FEATURES
# Stereo Headphone Power Amplifier : 50mW+50mW # Sixth-order 32fS Over Sampling & PWM # Internal 8fS Over Sampling Digital Filter # Sampling Frequency : 96kHz (Max.) # De-Emphasis : 32kHz, 44.1kHz, 48kHz # System Clock : 256fS # Digital Processing : Attenuator 107step, LOG Curve : Mute # Digital Audio Interface : 16bit, 18bit 2 : I S, LSB Justified, MSB Justified # Operating Voltage : 3.0 to 3.6V # Driving Voltage : VDD to 5.25V # C-MOS Technology # Package Outline : SSOP20
! PIN CONFIGURATION
STBY TEST VSSR OUT R VDDR VDDL OUT L VSSL MODE RST 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VDD F0/DATA F1/REQ F2/SCK MUTE DIN LRCK BCK MCK VSS
! BLOCK DIAGRAM
VDD VSS RST MCK LRCK BCK DIN MUTE STBY MODE F0/DATA F1/REQ F2/SCK
Power On Reset Circuit VDDL Synchronization Circuit Serial Audio Data Interface 8fS Over Sampling Digital Filter 32fS 6 & PWM
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OUT L VSSL
VDDR OUT R System Control VSSR
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NJU8721
! TERMINAL DESCRIPTION
No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 SYMBOL STBY TEST VSSR OUTR VDDR VDDL OUTL VSSL MODE RST VSS MCK BCK LRCK DIN MUTE F2/SCK F1/REQ F0/DATA VDD I/O I I - O - - O - I I - I I I I I I I I - FUNCTION Standby Control Terminal Low : Standby ON High : Standby OFF Manufacturer Testing Terminal Normally connect to GND. Rch Power GND, VSSR=0V Rch Output Terminal Rch Power Supply, VDDR=VDD to 5.0V Lch Power Supply, VDDL=VDD to 5.0V Lch Output terminal Lch Power GND, VSSL=0V Control Mode selection Terminal Low : Parallel Control Mode High : Serial Control Mode Reset Terminal Low : Reset ON High : Reset OFF Logic Power GND, VSS=0V Master Clock Input Terminal 256fS clock inputs this terminal. Serial Audio Data Bit Clock Input Terminal This clock must synchronize with MCK input signal. L/R Channel Clock Input Terminal This clock must synchronize with MCK input signal. Serial Audio Data Input Terminal Mute Control Terminal Low : Mute ON High : Mute OFF MODE="Low" : Serial Audio Interface Format Selection Terminal 2 MODE="High" : Control Register Data Shift Clock Input Terminal The data is fetched into the control register by rise edge of SCK signal. MODE="Low" : Serial Audio Interface Format Selection Terminal 1 MODE="High" : Control Register Data Request Input Terminal MODE="Low" : Serial Audio Interface Format Selection Terminal 0 MODE="High" : Control Register Data Input Terminal Logic Power Supply, VDD=3.3V
! INPUT TERMINAL STRUCTURE
VDD
Input Terminal VSS
Inside Circuit
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NJU8721
! FUNCTIONAL DESCRIPTION
(1) Signal Output PWM signals of L channel and R output from OUTL and OUTR terminals respectively. These signals are converted to analog signal by external 2nd-order or over LC filter. The output driver power supplied from VDDL, VDDR, VSSL, and VSSR are required high response power supply against voltage fluctuation like as switching regulator because Output THD is effected by power supply stability. (2) Master Clock Master Clock is 256fS clock into MCK terminal for the internal circuit operation clock. (3) Reset "L" level input over than 3ms to the RST terminal is initialization signal to initialize the internal circuit. This initialization signal is synchronized with internal clock and executes logical OR with the internal power on reset signal. This Reset signal initializes the internal function setting registers also. During initialization, the output-drivers output GND level. The reset equivalent circuit is shown bellow.
RST Power on Reset CLK (About 10kHz)
Internal Reset
D D D D D D D D
Figure 1. Reset Equivalent Circuit
(4) 8fS Over Sampling Digital Filter 8fS Over Sampling Digital Filter interpolates Audio data and decreases aliasing noise. It realizes Attenuation and De-Emphasis function by serial function control. (5) 32fS 6 & PWM th 32fS 6 & PWM convert from Audio data of the 8fS Over Sampling Digital Filter to the 32fS one bit PWM data.
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